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/freebsd/sys/dev/clk/
H A Dclk.c1 /*-
51 SYSCTL_NODE(_hw, OID_AUTO, clock, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
54 MALLOC_DEFINE(M_CLOCK, "clocks", "Clock framework");
64 /* Default clock methods. */
66 static int clknode_method_recalc_freq(struct clknode *clk, uint64_t *freq);
73 * Clock controller methods.
87 * Clock node - basic element for modeling SOC clock graph. It holds the clock
88 * provider's data about the clock, and the links for the clock's membership in
94 /* Clock nodes topology. */
95 struct clkdom *clkdom; /* Owning clock domain */
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H A Dclk_fixed.c1 /*-
53 static int clknode_fixed_recalc(struct clknode *clk, uint64_t *freq);
59 uint64_t freq; member
80 if (sc->freq == 0) in clknode_fixed_init()
86 clknode_fixed_recalc(struct clknode *clk, uint64_t *freq) in clknode_fixed_recalc() argument
92 if ((sc->mult != 0) && (sc->div != 0)) in clknode_fixed_recalc()
93 *freq = (*freq / sc->div) * sc->mult; in clknode_fixed_recalc()
95 *freq = sc->freq; in clknode_fixed_recalc()
106 if (sc->mult == 0 || sc->div == 0) { in clknode_fixed_set_freq()
107 /* Fixed frequency clock. */ in clknode_fixed_set_freq()
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H A Dclk.h1 /*-
38 #define CLKNODE_IDX_NONE -1 /* Not-selected index */
42 #define CLK_NODE_GLITCH_FREE 0x00000002 /* Freq can change w/o stop */
44 #define CLK_NODE_LINKED 0x00000008 /* Is linked clock */
79 * Clock domain functions.
88 * Clock providers interface.
114 int clknode_get_freq(struct clknode *clknode, uint64_t *freq);
115 int clknode_set_freq(struct clknode *clknode, uint64_t freq, int flags,
117 int clknode_test_freq(struct clknode *clknode, uint64_t freq, int flags,
124 * Clock consumers interface.
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/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-qcom-hw.txt8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
15 Value type: <phandle> From common clock binding.
16 Definition: clock handle for XO clock and GPLL0 clock.
18 - clock-names
20 Value type: <string> From common clock binding.
23 - reg
25 Value type: <prop-encoded-array>
28 - reg-names
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H A Dcpufreq-qcom-hw.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qco
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
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/freebsd/contrib/ntp/ntpd/
H A Dntp_loopfilter.c2 * ntp_loopfilter.c - implements the NTP loop filter algorithm
32 * This is an implementation of the clock discipline algorithm described
33 * in UDel TR 97-4-3, as amended. It operates as an adaptive parameter,
34 * hybrid phase/frequency-lock loop. A number of sanity checks are
41 #define CLOCK_PHI 15e-6 /* max frequency error (s/s) */
47 #define CLOCK_LIMIT 30 /* poll-adjust threshold */
48 #define CLOCK_PGATE 4. /* poll-adjust gate */
54 * Clock discipline state machine. This is used to control the
60 * NSET FREQ ste
1072 set_freq(double freq) set_freq() argument
1243 loop_config(int item,double freq) loop_config() argument
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/freebsd/sys/dev/qat/qat_common/
H A Dadf_clock.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
27 struct adf_hw_device_data *hw_data = accel_dev->hw_device; in adf_clock_debugfs_add()
34 device_get_sysctl_ctx(accel_dev->accel_pci_dev.pci_dev); in adf_clock_debugfs_add()
36 device_get_sysctl_tree(accel_dev->accel_pci_dev.pci_dev); in adf_clock_debugfs_add()
43 &hw_data->clock_frequency, in adf_clock_debugfs_add()
45 "clock frequency"); in adf_clock_debugfs_add()
51 * adf_dev_measure_clock() -- Measure the CPM clock frequency
92 "Excessive clock measure delay\n"); in measure_clock()
117 "Excessive clock measure delay\n"); in measure_clock()
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/freebsd/sys/arm/ti/omap4/
H A Domap4_prcm_clks.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
56 * This file defines the clock configuration for the OMAP4xxx series of
61 * - There is a top level omap_prcm module that defines all OMAP SoC drivers
65 * configuring the clock - this file is the 'donkey' for OMAP44xx devices.
67 * - The key bit in this file is the omap_clk_devmap array, it's
71 * - In essence you just need to define some callbacks for each of the
74 * - The other thing that is worth noting is that when the omap_prcm device
78 * individual clock callback handlers.
83 * is no longer a separate functional and interface clock for each module,
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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_cpufreq.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
50 uint64_t freq; /* Frequency point */ member
66 uint64_t freq; /* Frequecy */ member
72 {204000000UL, 1007452, -23865, 370},
73 {306000000UL, 1052709, -24875, 370},
74 {408000000UL, 1099069, -25895, 370},
75 {510000000UL, 1146534, -26905, 370},
76 {612000000UL, 1195102, -27915, 370},
77 {714000000UL, 1244773, -28925, 370},
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/freebsd/sys/dev/qcom_clk/
H A Dqcom_clk_rcg2.c1 /*-
52 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_CFG_REG)
54 ((sc)->cmd_rcgr + QCOM_CLK_RCG2_CMD_REG)
56 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_M_REG)
58 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_N_REG)
60 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_D_REG)
76 * Finish a clock update.
88 CLKDEV_READ_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
91 CLKDEV_WRITE_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
99 CLKDEV_READ_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Datmel,sama5d2-pdmic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/sound/atmel,sama5d2-pdmic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
20 const: atmel,sama5d2-pdmic
30 - description: peripheral clock
31 - description: generated clock
33 clock-names:
35 - const: pclk
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H A Datmel-pdmic.txt4 - compatible
5 Should be "atmel,sama5d2-pdmic".
6 - reg
8 - interrupts
10 - dmas
11 One DMA specifiers as described in atmel-dma.txt and dma.txt files.
12 - dma-names
14 - clock-names
16 - "pclk" peripheral clock
17 - "gclk" generated clock
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/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_cpufreq.c1 /*-
51 uint64_t freq; /* Frequency point */ member
67 uint64_t freq; /* Frequecy */ member
73 { 204000000ULL, 1112619, -29295, 402},
74 { 306000000ULL, 1150460, -30585, 402},
75 { 408000000ULL, 1190122, -31865, 402},
76 { 510000000ULL, 1231606, -33155, 402},
77 { 612000000ULL, 1274912, -34435, 402},
78 { 714000000ULL, 1320040, -35725, 402},
79 { 816000000ULL, 1366990, -37005, 402},
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/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca5s.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
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H A Dvexpress-v2p-ca15-tc1.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
8 * HBI-0237A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15";
18 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_cpufreq.c1 /*-
2 * Copyright (C) 2013-2015 Daisuke Aoyama <aoyama@peach.ne.jp>
61 #define HZ2MHZ(freq) ((freq) / (1000 * 1000)) argument
62 #define MHZ2HZ(freq) ((freq) * (1000 * 1000)) argument
71 #define MIN_OVER_VOLTAGE -16
73 #define MSG_ERROR -999999999
85 /* ARM->VC mailbox property semaphore */
115 { "broadcom,bcm2835-vc", 1 },
116 { "broadcom,bcm2708-vc", 1 },
158 * Get clock rate in bcm2835_cpufreq_get_clock_rate()
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/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
112 sc->dev = dev; in bhnd_pmu_attach()
113 sc->res = res; in bhnd_pmu_attach()
116 sc->caps = bhnd_bus_read_4(sc->res, BHND_PMU_CAP); in bhnd_pmu_attach()
118 /* Find the bus and bus-attached core */ in bhnd_pmu_attach()
120 core = sc->dev; in bhnd_pmu_attach()
129 device_printf(sc->dev, "bhnd bus not found\n"); in bhnd_pmu_attach()
134 sc->cid = *bhnd_get_chipid(core); in bhnd_pmu_attach()
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/freebsd/sys/dev/dwc/
H A Dif_dwc_rk.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
139 /* PHY clock */
167 {"rockchip,rk3288-gmac", (uintptr_t)&rk3288_ops},
168 {"rockchip,rk3328-gmac", (uintptr_t)&rk3328_ops},
169 {"rockchip,rk3399-gmac", (uintptr_t)&rk3399_ops},
179 if (!mii_contype_is_rgmii(sc->base.phy_mode)) in rk3328_set_delays()
182 reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON0); in rk3328_set_delays()
186 reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON1); in rk3328_set_delays()
188 device_printf(sc->base.dev, "current delays settings: tx=%u(%s) rx=%u(%s)\n", in rk3328_set_delays()
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/freebsd/sys/dev/bhnd/cores/chipc/pwrctl/
H A Dbhnd_pwrctl.h1 /*-
38 * Request that @p clock (or a faster clock) be enabled on behalf of
43 * @param clock Clock requested.
46 * @retval ENODEV If an unsupported clock was requested.
49 bhnd_pwrctl_request_clock(device_t dev, device_t child, bhnd_clock clock) in bhnd_pwrctl_request_clock() argument
51 return (BHND_PWRCTL_REQUEST_CLOCK(dev, child, clock)); in bhnd_pwrctl_request_clock()
55 * Return the transition latency required for @p clock in microseconds, if
62 * @param clock The clock to be queried for transition latency.
63 * @param[out] latency On success, the transition latency of @p clock in
67 * @retval ENODEV If the transition latency for @p clock is not available.
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/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Dsamsung,s3c2410-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/samsung,s3c2410-i2
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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/freebsd/sys/arm64/qoriq/clk/
H A Dqoriq_clkgen.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
55 { -1, 0 }
96 if (sc->flags & QORIQ_LITTLE_ENDIAN) in qoriq_clkgen_write_4()
97 bus_write_4(sc->res, addr, htole32(val)); in qoriq_clkgen_write_4()
99 bus_write_4(sc->res, addr, htobe32(val)); in qoriq_clkgen_write_4()
110 if (sc->flags & QORIQ_LITTLE_ENDIAN) in qoriq_clkgen_read_4()
111 *val = le32toh(bus_read_4(sc->res, addr)); in qoriq_clkgen_read_4()
113 *val = be32toh(bus_read_4(sc->res, addr)); in qoriq_clkgen_read_4()
126 if (sc->flags & QORIQ_LITTLE_ENDIAN) in qoriq_clkgen_modify_4()
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/freebsd/sys/powerpc/cpufreq/
H A Dpmufreq.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 if (OF_getprop(node, "min-clock-frequency", &min_freq, sizeof(min_freq)) == -1) in pmufreq_identify()
92 if (device_find_child(parent, "pmufreq", -1) != NULL) in pmufreq_identify()
99 if (BUS_ADD_CHILD(parent, 10, "pmufreq", -1) == NULL) in pmufreq_identify()
114 * A scalable MPC7455 has min-clock-frequency/max-clock-frequency as OFW in pmufreq_probe()
117 if (OF_getprop(node, "min-clock-frequency", &min_freq, sizeof(min_freq)) == -1) in pmufreq_probe()
119 device_set_desc(dev, "PMU-based frequency scaling"); in pmufreq_probe()
130 sc->dev = dev; in pmufreq_attach()
133 OF_getprop(node, "min-clock-frequency", &sc->minfreq, sizeof(sc->minfreq)); in pmufreq_attach()
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