/freebsd/sys/contrib/device-tree/Bindings/mmc/ |
H A D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd) 7 and the properties used by the sdhci-sprd driver. 10 - compatible: Should contain "sprd,sdhci-r11". 11 - reg: physical base address of the controller and length. 12 - interrupts: Interrupts used by the SDHCI controller. 13 - clocks: Should contain phandle for the clock feeding the SDHCI controller 14 - clock-names: Should contain the following: 15 "sdio" - SDIO source clock (required) 16 "enable" - gate clock which used for enabling/disabling the device (required) 17 "2x_enable" - gate clock controlling the device for some special platforms (optional) [all …]
|
H A D | sprd,sdhci-r11.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Orson Zhai <orsonzhai@gmail.com> 11 - Baolin Wang <baolin.wang7@gmail.com> 12 - Chunyan Zhang <zhang.lyra@gmail.com> 16 const: sprd,sdhci-r11 27 - description: SDIO source clock 28 - description: gate clock for enabling/disabling the device [all …]
|
H A D | mtk-sd.txt | 10 - compatible: value should be either of the following. 11 "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135 12 "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 13 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183 14 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516 15 "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779 16 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 17 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 18 "mediatek,mt7622-mmc": for MT7622 SoC 19 "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC [all …]
|
H A D | mtk-sd.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chaotian Jing <chaotian.jing@mediatek.com> 11 - Wenbi [all...] |
H A D | fsl-imx-esdhc.txt | 7 by mmc.txt and the properties used by the sdhci-esdhc-imx driver. 10 - compatible : Should be "fsl,<chip>-esdhc", the supported chips include 11 "fsl,imx25-esdhc" 12 "fsl,imx35-esdhc" 13 "fsl,imx51-esdhc" 14 "fsl,imx53-esdhc" 15 "fsl,imx6q-usdhc" 16 "fsl,imx6sl-usdhc" 17 "fsl,imx6sx-usdhc" 18 "fsl,imx6ull-usdhc" [all …]
|
H A D | sdhci-am654.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 4 --- 5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Ulf Hansson <ulf.hansson@linaro.org> 14 - $ref: sdhci-common.yaml# 19 - enum: 20 - ti,am62-sdhci 21 - ti,am64-sdhci-4bit [all …]
|
/freebsd/sys/contrib/device-tree/Bindings/net/ |
H A D | mediatek-dwmac.txt | 9 - compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC 10 - reg: Address and length of the register set for the device 11 - interrupts: Should contain the MAC interrupts 12 - interrupt-names: Should contain a list of interrupt names corresponding to 15 - clocks: Must contain a phandle for each entry in clock-names. 16 - clock-names: The name of the clock listed in the clocks property. These are 18 - mac-address: See ethernet.txt in the same directory 19 - phy-mode: See ethernet.txt in the same directory 20 - mediatek,pericfg: A phandle to the syscon node that control ethernet 21 interface and timing delay. [all …]
|
H A D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Neil Armstrong <neil.armstrong@linaro.org> 12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com> 20 - amlogic,meson6-dwmac 21 - amlogic,meson8b-dwmac 22 - amlogic,meson8m2-dwmac 23 - amlogic,meson-gxbb-dwmac [all …]
|
H A D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schema [all...] |
H A D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+ 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Alexandru Tachici <alexandru.tachici@analog.com> 16 - $ref: ethernet-phy.yaml# 19 adi,rx-internal-delay-ps: 21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with 22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. 26 adi,tx-internal-delay-ps: 28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with [all …]
|
H A D | fsl,fec.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shawn Guo <shawnguo@kernel.org> 11 - Wei Fang <wei.fang@nxp.com> 12 - NXP Linux Team <linux-imx@nxp.com> 15 - $ref: ethernet-controller.yaml# 20 - enum: 21 - fsl,imx25-fec 22 - fsl,imx27-fec [all …]
|
H A D | mediatek-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/mediatek-dwma [all...] |
H A D | renesas,etheravb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sergei Shtylyov <sergei.shtylyov@gmail.com> 15 - items: 16 - enum: 17 - renesas,etheravb-r8a7742 # RZ/G1H 18 - renesas,etheravb-r8a7743 # RZ/G1M 19 - renesas,etheravb-r8a7744 # RZ/G1N 20 - renesas,etheravb-r8a7745 # RZ/G1E [all …]
|
H A D | ingenic,mac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 18 - ingenic,jz4775-mac 19 - ingenic,x1000-mac 20 - ingenic,x1600-mac 21 - ingenic,x1830-mac 22 - ingenic,x2000-mac 30 interrupt-names: [all …]
|
/freebsd/sys/contrib/device-tree/Bindings/c6x/ |
H A D | clocks.txt | 1 C6X PLL Clock Controllers 2 ------------------------- 4 This is a first-cut support for the SoC clock controllers. This is still 6 clock support is added to the kernel. 10 - compatible: "ti,c64x+pll" 11 May also have SoC-specific value to support SoC-specific initialization 13 "ti,c6455-pll" 14 "ti,c6457-pll" 15 "ti,c6472-pll" 16 "ti,c6474-pll" [all …]
|
/freebsd/contrib/ntp/html/ |
H A D | stats.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> 4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1"> 12 <!-- #BeginDate format:En2m -->26-Jul-2015 06:29<!-- #EndDate --> 28 …<li>Nominal estimate of the server clock time relative to the client clock time. This is called <e… 29 …<li>Roundtrip system and network delay measured by the on-wire protocol. This is call <em>roundtri… 30 …<li>Potential clock offset error due to the maximum uncorrected system clock frequency error. This… 31 …<li>Expected error, consisting of the root mean square (RMS) nominal clock offset sample differenc… 38 …he server. The data represented in boxes labeled Peer are computed by the on-wire protocol, as des… 40 …delay δ samples measured by the on-wire protocol, as described on the <a href="warp.html">Ho… 42 …clock frequency is not within 1 PPM or so of the the server clock frequency, the roundtrip delay m… [all …]
|
H A D | filter.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> 4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1"> 6 <title>Clock Filter Algorithm</title> 10 <h3>Clock Filter Algorithm</h3> 12 <!-- #BeginDate format:En2m -->10-Mar-2014 05:05<!-- #EndDate --> 15 <p>The clock filter algorithm processes the offset and delay samples produced by the on-wire protoc… 19 …delay collected over a 24-hr period. As the delay increases, the offset variation increases, so … 20 …clock filter algorithm works best when the delays are statistically identical in the reciprocal … 21 …clock filter algorithm the offset and delay samples from the on-wire protocol are inserted as th… 22 <p>In each peer process the clock filter algorithm selects the stage with the smallest delay, wh… [all …]
|
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
H A D | fsl,cpm1-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: PowerQUICC CPM Time-slot assigner (TSA) controller 10 - Herve Codina <herve.codina@bootlin.com> 13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. 14 Its purpose is to route some TDM time-slots to other internal serial 20 - enum: 21 - fsl,mpc885-tsa [all …]
|
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
H A D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from 8 - reg: Must contains offset/length value for controller. 10 - #address-cells: Must be 2. The partition number has to be encoded in the 11 first address cell and it may accept values 0..N-1 12 (N - total number of partitions). The second cell is the 15 - #size-cells: Must be set to 1. 17 - ranges: Must contain one or more chip select memory regions. 19 - clocks: Must contain references to controller clocks. 21 - clock-names: Must contain "mpmcclk" and "apb_pclk". 23 - clock-ranges: Empty property indicating that child nodes can inherit [all …]
|
/freebsd/sys/contrib/device-tree/Bindings/spi/ |
H A D | renesas,sh-msiof.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Geert Uytterhoeven <geert+renesas@glider.be> 13 - $ref: spi-controller.yaml# 18 - items: 19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5 20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible 22 - items: [all …]
|
H A D | spi-fsl-dspi.txt | 4 - compatible : must be one of: 5 "fsl,vf610-dspi", 6 "fsl,ls1021a-v1.0-dspi", 7 "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), 8 "fsl,ls1028a-dspi", 9 "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), 10 "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), 11 "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), 12 "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"), 13 "fsl,ls2085a-dspi", [all …]
|
/freebsd/sys/contrib/device-tree/Bindings/sound/ |
H A D | rt5682.txt | 7 - compatible : "realtek,rt5682" or "realtek,rt5682i" 9 - reg : The I2C address of the device. 11 - AVDD-supply: phandle to the regulator supplying analog power through the 14 - MICVDD-supply: phandle to the regulator supplying power for the microphone 17 - VBAT-supply: phandle to the regulator supplying battery power through the 20 - DBVDD-supply: phandle to the regulator supplying I/O power through the DBVDD 23 - LDO1-IN-supply: phandle to the regulator supplying power to the digital core 28 - interrupts : The CODEC's interrupt output. 30 - realtek,dmic1-data-pin 35 - realtek,dmic1-clk-pin [all …]
|
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/ |
H A D | jedec,lpddr3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3 10 - Krzysztof Kozlowski <krzk@kernel.org> 13 - $ref: jedec,lpddr-props.yaml# 18 - items: 19 - enum: 20 - samsung,K3QF2F20DB [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/exynos/ |
H A D | exynos7-espresso.dts | 1 // SPDX-License-Identifier: GPL-2.0 9 /dts-v1/; 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/clock/samsung,s2mps11.h> 13 #include <dt-bindings/gpio/gpio.h> 17 compatible = "samsung,exynos7-espresso", "samsung,exynos7"; 26 stdout-path = &serial_2; 34 usb30_vbus_reg: regulator-usb30 { 35 compatible = "regulator-fixed"; 36 regulator-name = "VBUS_5V"; [all …]
|
/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | imx8qm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/pinctrl/pads-imx8qm.h> 12 #include <dt-bindings/thermal/thermal.h> 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; [all …]
|