/linux/Documentation/devicetree/bindings/clock/ |
H A D | mediatek,mt8195-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MediaTek Functional Clock Controller for MT8195 10 - Chun-Jie Chen <chun-jie.chen@mediatek.com> 13 The clock architecture in Mediatek like below 14 PLLs --> 15 dividers --> 17 --> [all …]
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H A D | mediatek,mt8192-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MediaTek Functional Clock Controller for MT8192 10 - Chun-Jie Chen <chun-jie.chen@mediatek.com> 13 The Mediatek functional clock controller provides various clocks on MT8192. 18 - enum: 19 - mediatek,mt8192-scp_adsp 20 - mediatek,mt8192-imp_iic_wrap_c [all …]
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H A D | pistachio-clock.txt | 1 Imagination Technologies Pistachio SoC clock controllers 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral 6 from the device-tree. 9 ---------------- 11 There are three external inputs to the clock controllers which should be 12 defined with the following clock-output-names: 13 - "xtal": External 52Mhz oscillator (required) 14 - "audio_clk_in": Alternate audio reference clock (optional) 15 - "enet_clk_in": Alternate ethernet PHY clock (optional) 17 Core clock controller: [all …]
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H A D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller 3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which 10 clk_sysbypck are inputs to the clock controller. 12 network. They are set on the device tree, but not used by the clock module. The 17 dt-bindings/clock/nuvoton,npcm7xx-clock.h 20 Required Properties of clock controller: 22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton 25 - reg: physical base address of the clock controller and length of 28 - #clock-cells: should be 1. 30 Example: Clock controller node: [all …]
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/linux/drivers/clk/samsung/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 4 bool "Samsung Exynos clock controller support" if COMPILE_TEST 18 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST 21 Support for the clock controller present on the Samsung S3C64xx SoCs. 25 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST 28 Support for the clock controller present on the Samsung S5Pv210 SoCs. 32 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST 35 Support for the clock controller present on the Samsung 39 bool "Samsung Exynos4 clock controller support" if COMPILE_TEST 42 Support for the clock controller present on the Samsung [all …]
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/linux/drivers/clk/meson/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 2 menu "Clock support for Amlogic platforms" 56 bool "Meson8 SoC Clock controller support" 66 Support for the clock controller on AmLogic S802 (Meson8), 71 tristate "GXBB and GXL SoC clock controllers support" 83 Support for the clock controller on AmLogic S905 devices, aka gxbb. 87 tristate "AXG SoC clock controllers support" 98 Support for the clock controller on AmLogic A113D devices, aka axg. 102 tristate "Meson AXG Audio Clock Controller Driver" 111 Support for the audio clock controller on AmLogic A113D devices, [all …]
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/linux/arch/arm/boot/dts/hisilicon/ |
H A D | hisi-x5hd2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2013-2014 Linaro Ltd. 4 * Copyright (c) 2013-2014 HiSilicon Limited. 7 #include <dt-bindings/clock/hix5hd2-clock.h> 10 #address-cells = <1>; 11 #size-cells = <1>; 17 gic: interrupt-controller@f8a01000 { 18 compatible = "arm,cortex-a9-gic"; 19 #interrupt-cells = <3>; 20 #address-cells = <0>; [all …]
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H A D | hi3620.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2012-2013 HiSilicon Ltd. 6 * Copyright (C) 2012-2013 Linaro Ltd. 11 #include <dt-bindings/clock/hi3620-clock.h> 14 #address-cells = <1>; 15 #size-cells = <1>; 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <26000000>; 29 clock-output-names = "apb_pclk"; [all …]
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/linux/drivers/clk/sophgo/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 2 # common clock support for SOPHGO SoC family. 5 tristate "Support for the Sophgo CV1800 series SoCs clock controller" 8 This driver supports clock controller of Sophgo CV18XX series SoC. 9 The driver require a 25MHz Oscillator to function generate clock. 10 It includes PLLs, common clock function and some vendor clock for 14 tristate "Sophgo SG2042 PLL clock support" 17 This driver supports the PLL clock controller on the 18 Sophgo SG2042 SoC. This clock IP uses three oscillators with 23 tristate "Sophgo SG2042 Clock Generator support" [all …]
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/linux/arch/arm64/boot/dts/hisilicon/ |
H A D | hi3670.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/clock/hi3670-clock.h> 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 19 compatible = "arm,psci-0.2"; 24 #address-cells = <2>; 25 #size-cells = <0>; 27 cpu-map { [all …]
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H A D | hi3660.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/hi3660-clock.h> 10 #include <dt-bindings/thermal/thermal.h> 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 19 compatible = "arm,psci-0.2"; 24 #address-cells = <2>; 25 #size-cells = <0>; [all …]
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/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8-ss-lsio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2020 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 10 lsio_bus_clk: clock-lsio-bus { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <100000000>; 14 clock-output-names = "lsio_bus_clk"; 18 compatible = "simple-bus"; [all …]
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H A D | imx8-ss-mipi0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only and MIT 8 compatible = "simple-bus"; 9 interrupt-parent = <&irqsteer_mipi0>; 10 #address-cells = <1>; 11 #size-cells = <1>; 14 irqsteer_mipi0: interrupt-controller@56220000 { 15 compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer"; 18 interrupt-controller; 19 interrupt-parent = <&gic>; 20 #interrupt-cells = <1>; [all …]
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H A D | imx8-ss-mipi1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only and MIT 8 compatible = "simple-bus"; 9 interrupt-parent = <&irqsteer_mipi1>; 10 #address-cells = <1>; 11 #size-cells = <1>; 14 irqsteer_mipi1: interrupt-controller@57220000 { 15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; 18 interrupt-controller; 19 interrupt-parent = <&gic>; 20 #interrupt-cells = <1>; [all …]
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/linux/include/soc/canaan/ |
H A D | k210-sysctl.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 10 * Kendryte K210 SoC system controller registers offsets. 11 * Taken from Kendryte SDK (kendryte-standalone-sdk). 15 #define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */ 16 #define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */ 17 #define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */ 20 #define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */ 21 #define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */ 22 #define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */ [all …]
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/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt6779.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 8 #include <dt-bindings/clock/mt6779-clk.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/pinctrl/mt6779-pinfunc.h> 15 interrupt-parent = <&sysirq>; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 compatible = "arm,psci-0.2"; 25 #address-cells = <1>; [all …]
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/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/ |
H A D | sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Hisilicon system controller 10 - Wei Xu <xuwei5@hisilicon.com> 13 The Hisilicon system controller is used on many Hisilicon boards, it can be 16 There are some variants of the Hisilicon system controller, such as HiP01, 17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the 18 Hisilicon system controller, but some same registers located at different [all …]
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/linux/arch/mips/boot/dts/ingenic/ |
H A D | jz4740.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 3 #include <dt-bindings/clock/ingenic,tcu.h> 6 #address-cells = <1>; 7 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 16 compatible = "ingenic,xburst-mxu1.0"; 20 clock-names = "cpu"; 24 cpuintc: interrupt-controller { [all …]
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H A D | jz4770.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h> 3 #include <dt-bindings/clock/ingenic,tcu.h> 6 #address-cells = <1>; 7 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 16 compatible = "ingenic,xburst-fpu1.0-mxu1.1"; 20 clock-names = "cpu"; 24 cpuintc: interrupt-controller { [all …]
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H A D | jz4725b.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h> 3 #include <dt-bindings/clock/ingenic,tcu.h> 6 #address-cells = <1>; 7 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 16 compatible = "ingenic,xburst-mxu1.0"; 20 clock-names = "cpu"; 24 cpuintc: interrupt-controller { [all …]
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H A D | x1000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ingenic,tcu.h> 3 #include <dt-bindings/clock/ingenic,x1000-cgu.h> 4 #include <dt-bindings/dma/x1000-dma.h> 7 #address-cells = <1>; 8 #size-cells = <1>; 12 #address-cells = <1>; 13 #size-cells = <0>; 17 compatible = "ingenic,xburst-fpu1.0-mxu1.1"; 21 clock-names = "cpu"; [all …]
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/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos5260.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/clock/exynos5260-clk.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 34 #address-cells = <1>; 35 #size-cells = <0>; 37 cpu-map { [all …]
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imxrt1050.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "../../armv7-m.dtsi" 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/imxrt1050-clock.h> 10 #include <dt-bindings/gpio/gpio.h> 13 #address-cells = <1>; 14 #size-cells = <1>; 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <24000000>; [all …]
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/linux/drivers/clk/starfive/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 7 bool "StarFive JH7100 clock support" 12 Say yes here to support the clock controller on the StarFive JH7100 16 tristate "StarFive JH7100 audio clock support" 25 bool "StarFive JH7110 PLL clock support" 29 Say yes here to support the PLL clock controller on the 33 bool "StarFive JH7110 system clock support" 41 Say yes here to support the system clock controller on the 45 tristate "StarFive JH7110 always-on clock support" 49 Say yes here to support the always-on clock controller on the [all …]
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/linux/Documentation/devicetree/bindings/media/ |
H A D | microchip,csi2dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip CSI2 Demux Controller (CSI2DC) 10 - Eugen Hristev <eugen.hristev@microchip.com> 13 CSI2DC - Camera Serial Interface 2 Demux Controller 19 clock domain towards a parallel interface that can be read by a sensor 20 controller. 26 is connected at the output to a sensor controller and the data pipe is 27 accessible as a DMA slave port to a DMA controller. [all …]
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