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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 cpu0_opp_table: opp-table-cpu0 {
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp-216000000-750 {
9 clock-latency-ns = <400000>;
10 opp-supported-hw = <0x0F 0x0003>;
11 opp-hz = /bits/ 64 <216000000>;
12 opp-suspend;
15 opp-216000000-800 {
[all …]
H A Dtegra30-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 cpu0_opp_table: opp-table-cpu0 {
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp-51000000-800 {
9 clock-latency-ns = <100000>;
10 opp-supported-hw = <0x1F 0x31FE>;
11 opp-hz = /bits/ 64 <51000000>;
14 opp-51000000-850 {
15 clock-latency-ns = <100000>;
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm23550.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
8 #include "bcm2166x-common.dtsi"
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
21 clock-frequency = <1000000000>;
26 compatible = "arm,cortex-a7";
27 enable-method = "brcm,bcm23550";
28 secondary-boot-reg = <0x35004178>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
58 compatible = "arm,cortex-a7";
60 clocks = <&clock CLK_KFC_CLK>;
61 clock-frequency = <1000000000>;
[all …]
H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
59 compatible = "arm,cortex-a15";
61 clocks = <&clock CLK_ARM_CLK>;
62 clock-frequency = <1800000000>;
[all …]
H A Dexynos4212.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
39 compatible = "arm,cortex-a9";
41 clocks = <&clock CLK_ARM_CLK>;
42 clock-names = "cpu";
43 operating-points-v2 = <&cpu0_opp_table>;
44 #cooling-cells = <2>; /* min followed by max */
49 compatible = "arm,cortex-a9";
[all …]
H A Dexynos5800.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 &clock {
20 compatible = "samsung,exynos5800-clock", "syscon";
24 opp-2000000000 {
25 opp-hz = /bits/ 64 <2000000000>;
26 opp-microvolt = <1312500 1312500 1500000>;
27 clock-latency-ns = <140000>;
29 opp-1900000000 {
30 opp-hz = /bits/ 64 <1900000000>;
31 opp-microvolt = <1262500 1262500 1500000>;
[all …]
H A Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
45 compatible = "arm,cortex-a9";
47 clocks = <&clock CLK_ARM_CLK>;
48 clock-names = "cpu";
49 operating-points-v2 = <&cpu0_opp_table>;
50 #cooling-cells = <2>; /* min followed by max */
55 compatible = "arm,cortex-a9";
[all …]
/linux/tools/testing/selftests/mqueue/
H A Dmq_perf_tests.c47 " %s [-c #[,#..] -f] path\n"
49 " -c # Skip most tests and go straight to a high queue depth test\n"
59 " -f Only usable with continuous mode. Pin ourself to the CPUs\n"
99 mqd_t queue = -1;
120 "re-run the tests using fake mode in order to check "
136 "the no-mqueue work and mqueue work tests",
192 if (queue != -1) in shutdown()
283 * open_queue - open the global queue for testing
284 * @attr - An attr struct specifying the desired queue traits
285 * @result - An attr struct that lists the actual traits the queue has
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dgated-fixed-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/gated-fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Gated Fixed clock
10 - Heiko Stuebner <heiko@sntech.de>
14 const: gated-fixed-clock
16 "#clock-cells":
19 clock-frequency: true
21 clock-output-names:
[all …]
H A Dnvidia,tegra124-car.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Clock and Reset Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
18 the clock source programming and most of the clock dividers.
20 CLKGEN input signals include the external clock for the reference frequency
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-s922x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-1000000000 {
15 opp-hz = /bits/ 64 <1000000000>;
16 opp-microvolt = <731000>;
17 clock-latency-ns = <50000>;
20 opp-1200000000 {
[all …]
H A Dmeson-g12b-a311d.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-1000000000 {
15 opp-hz = /bits/ 64 <1000000000>;
16 opp-microvolt = <761000>;
17 clock-latency-ns = <50000>;
20 opp-1200000000 {
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-overdrive.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
6 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
7 assigned-clock-rates = <0>, <1000000000>;
11 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
13 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
14 assigned-clock-rates = <0>, <1000000000>;
18 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
22 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
25 assigned-clock-rates = <750000000>,
/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-infinity2m.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include "mstar-infinity.dtsi"
10 opp-1000000000 {
11 opp-hz = /bits/ 64 <1000000000>;
12 opp-microvolt = <1000000>;
13 clock-latency-ns = <300000>;
16 opp-1200000000 {
17 opp-hz = /bits/ 64 <1200000000>;
18 opp-microvolt = <1000000>;
19 clock-latency-ns = <300000>;
[all …]
/linux/drivers/net/ethernet/cavium/common/
H A Dcavium_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* cavium_ptp.c - PTP 1588 clock on Cavium hardware
3 * Copyright (c) 2003-2015, 2017 Cavium, Inc.
67 return ERR_PTR(-ENODEV); in cavium_ptp_get()
71 ptp = ERR_PTR(-EPROBE_DEFER); in cavium_ptp_get()
83 pci_dev_put(ptp->pdev); in cavium_ptp_put()
88 * cavium_ptp_adjfine() - Adjust ptp frequency
89 * @ptp_info: PTP clock info
95 struct cavium_ptp *clock = in cavium_ptp_adjfine() local
104 scaled_ppm = -scaled_ppm; in cavium_ptp_adjfine()
[all …]
/linux/arch/mips/cavium-octeon/
H A Doct_ilm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <asm/octeon/cvmx-ciu-defs.h>
38 max = (curr_li.max_latency * 1000000000) / cpuclk; in oct_ilm_show()
39 min = (curr_li.min_latency * 1000000000) / cpuclk; in oct_ilm_show()
40 avg = (curr_li.latency_sum * 1000000000) / (cpuclk * curr_li.interrupt_cnt); in oct_ilm_show()
71 /* Calculating by the amounts io clock and cpu clock would in init_latency_info()
74 li->io_interval = (octeon_get_io_clock_rate() * interval) / 1000; in init_latency_info()
75 li->cpu_interval = (octeon_get_clock_rate() * interval) / 1000; in init_latency_info()
77 li->timer_start1 = 0; in init_latency_info()
78 li->timer_start2 = 0; in init_latency_info()
[all …]
/linux/arch/alpha/kernel/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0
8 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
10 * 1997-01-09 Adrian Sun
12 * 1997-10-29 John Bowman (bowman@math.ualberta.ca)
14 * (round system clock to nearest tick instead of truncating)
15 * fixed algorithm in time_init for getting time from CMOS clock
16 * 1999-04-16 Thorsten Kranzkowski (dl8bcu@gmx.net)
19 * 2003-06-03 R. Scott Bailey <scott.bailey@eds.com>
98 ce->event_handler(ce); in rtc_timer_interrupt()
112 return -EINVAL; in rtc_ce_set_next_event()
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 cluster0_opp_table: opp-table-cluster0 {
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp-1008000000 {
9 opp-hz = /bits/ 64 <1008000000>;
10 opp-microvolt = <675000 675000 950000>;
11 clock-latency-ns = <40000>;
13 opp-1200000000 {
14 opp-hz = /bits/ 64 <1200000000>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am625.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 i-cache-size = <0x8000>;
[all …]
H A Dk3-am62a7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62a.dtsi"
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 i-cache-size = <0x8000>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dwhite-hawk-ard-audio-da7212.dtso1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for White Hawk (Single) board with ARD-AUDIO-DA7212 board
5 * You can find and buy "ARD-AUDIO-DA7212" at Digi-Key
7 * https://www.digikey.jp/en/products/detail/ARD-AUDIO-DA7212/1564-1021-ND/5456357
14 * White Hawk ARD-AUDIO-DA7212
15 * +----------------------------+
19 * | AUDIO_CLKIN_V pin1 |<--\ +---------------+
20 * |(*) GP1_25/SL_SW2_V pin2 |<--/ |J2 |
21 * | AUDIO_CLKOUT_V pin5 |<----->| pin7 MCLK |
22 * | SSI_SCK_V pin9 |<----->| pin1 BCLK |
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
26 clock-names:
28 - const: dmc_clk
30 operating-points-v2: true
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/tegra114-car.h>
14 #include <dt-bindings/reset/nvidia,tegra114-car.h>
17 #include "clk-id.h"
21 #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
22 #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
113 /* Tegra CPU clock and reset control regs */
399 { 12000000, 1000000000, 1000, 12, 1, 12 },
400 { 13000000, 1000000000, 1000, 13, 1, 12 },
[all …]

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