Lines Matching +full:clock +full:- +full:1000000000

1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/tegra114-car.h>
16 #include "clk-id.h"
20 #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
21 #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
112 /* Tegra CPU clock and reset control regs */
398 { 12000000, 1000000000, 1000, 12, 1, 12 },
399 { 13000000, 1000000000, 1000, 13, 1, 12 },
400 { 19200000, 1000000000, 625, 12, 1, 12 },
401 { 26000000, 1000000000, 1000, 26, 1, 12 },
411 .vco_max = 1000000000,
429 .vco_max = 1000000000,
486 { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
487 { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
488 { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
489 { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
490 { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
556 .input_max = 1000000000,
585 .input_max = 1000000000,
613 #define MASK(x) (BIT(x) - 1)
870 { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
1059 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, in tegra114_periph_clk_init()
1067 clks[data->clk_id] = clk; in tegra114_periph_clk_init()
1074 /* Tegra114 CPU clock and reset control functions */
1126 { .compatible = "nvidia,tegra114-pmc" },
1180 * tegra114_car_barrier - wait for pending writes to the CAR to complete
1192 * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
1194 * When the CPU rail voltage is in the high-voltage range, use the
1195 * built-in hardwired clock propagation delays in the CPU clock
1202 /* Use hardwired rise->rise & fall->fall clock propagation delays */ in tegra114_clock_tune_cpu_trimmers_high()
1213 * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
1215 * When the CPU rail voltage is in the low-voltage range, use the
1216 * extended clock propagation delays set by
1218 * maintain the input clock duty cycle that the FCPU subsystem
1226 * Use software-specified rise->rise & fall->fall clock in tegra114_clock_tune_cpu_trimmers_low()
1240 * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
1242 * Program extended clock propagation delays into the FCPU clock
1243 * shaper and enable them. XXX Define the purpose - peak current
1251 /* Increment the rise->rise clock delay by four steps */ in tegra114_clock_tune_cpu_trimmers_init()
1258 * Use the rise->rise clock propagation delay specified in the in tegra114_clock_tune_cpu_trimmers_init()
1271 * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1287 * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1354 CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);