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/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
144 clkmgr: clock-controller@10d10000 { label
145 compatible = "intel,agilex5-clkmgr";
157 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
168 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
179 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
190 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
201 clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
211 clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
221 clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
[all …]
H A Dsocfpga_agilex.dtsi160 clkmgr: clock-controller@ffd10000 { label
161 compatible = "intel,agilex-clkmgr";
179 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
197 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
215 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
267 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
278 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
289 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
300 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
311 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
[all …]
H A Dsocfpga_n5x_socdk.dts37 &clkmgr {
38 compatible = "intel,easic-n5x-clkmgr";
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi165 clkmgr: clock-controller@ffd10000 { label
166 compatible = "intel,stratix10-clkmgr";
179 clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
197 clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
215 clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
272 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
283 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
294 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
305 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
316 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
[all …]
H A Dsocfpga_stratix10_swvp.dts98 clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
103 clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
/linux/Documentation/devicetree/bindings/clock/
H A Dintel,agilex5-clkmgr.yaml4 $id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
18 const: intel,agilex5-clkmgr
35 clkmgr: clock-controller@10d10000 {
36 compatible = "intel,agilex5-clkmgr";
H A Dintel,agilex.yaml18 const: intel,agilex-clkmgr
40 clkmgr: clock-controller@ffd10000 {
41 compatible = "intel,agilex-clkmgr";
H A Dintel,easic-n5x.yaml18 const: intel,easic-n5x-clkmgr
40 clkmgr: clock-controller@ffd10000 {
41 compatible = "intel,easic-n5x-clkmgr";
H A Dintel,stratix10.yaml14 const: intel,stratix10-clkmgr
32 compatible = "intel,stratix10-clkmgr";
/linux/sound/soc/codecs/
H A Des8311.c529 unsigned int clkmgr = ES8311_CLKMGR1_MCLK_ON; in es8311_hw_params() local
540 clkmgr = ES8311_CLKMGR1_MCLK_SEL; in es8311_hw_params()
555 clkmgr |= ES8311_CLKMGR1_BCLK_ON; in es8311_hw_params()
556 snd_soc_component_update_bits(component, ES8311_CLKMGR1, mask, clkmgr); in es8311_hw_params()
583 clkmgr = (coeff.div - 1) << ES8311_CLKMGR2_DIV_PRE_SHIFT | in es8311_hw_params()
585 snd_soc_component_update_bits(component, ES8311_CLKMGR2, mask, clkmgr); in es8311_hw_params()
588 clkmgr = (coeff.div_adc_dac - 1) << ES8311_CLKMGR5_ADC_DIV_SHIFT | in es8311_hw_params()
590 snd_soc_component_update_bits(component, ES8311_CLKMGR5, mask, clkmgr); in es8311_hw_params()
600 clkmgr = (div_lrclk - 1) >> 8; in es8311_hw_params()
602 clkmgr); in es8311_hw_params()
[all …]
/linux/Documentation/devicetree/bindings/arm/altera/
H A Dsocfpga-clk-manager.yaml28 clkmgr@ffd04000 {
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria5.dtsi13 clkmgr@ffd04000 {
H A Dsocfpga_cyclone5.dtsi13 clkmgr@ffd04000 {
H A Dsocfpga_vt.dts24 clkmgr@ffd04000 {
H A Dsocfpga_arria10_socdk.dtsi59 clkmgr@ffd04000 {
H A Dsocfpga_arria10.dtsi91 clkmgr@ffd04000 {
H A Dsocfpga.dtsi116 clkmgr@ffd04000 {
/linux/drivers/clk/socfpga/
H A Dclk-agilex.c546 { .compatible = "intel,agilex-clkmgr",
548 { .compatible = "intel,easic-n5x-clkmgr",
556 .name = "agilex-clkmgr",
H A Dclk-s10.c433 { .compatible = "intel,stratix10-clkmgr",
441 .name = "stratix10-clkmgr",