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/linux/drivers/iio/frequency/
H A Dadf4371.c1 // SPDX-License-Identifier: GPL-2.0
84 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
86 /* MOD2 is the programmable, 14-bit auxiliary fractional modulus */
199 val = (((u64)st->integer * ADF4371_MODULUS1) + st->fract1) * st->fpfd; in adf4371_pll_fract_n_get_rate()
200 tmp = (u64)st->fract2 * st->fpfd; in adf4371_pll_fract_n_get_rate()
201 do_div(tmp, st->mod2); in adf4371_pll_fract_n_get_rate()
205 ref_div_sel = st->rf_div_sel; in adf4371_pll_fract_n_get_rate()
259 return -EINVAL; in adf4371_set_freq()
261 st->rf_div_sel = 0; in adf4371_set_freq()
265 st->rf_div_sel++; in adf4371_set_freq()
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H A Dadmv1013.c1 // SPDX-License-Identifier: GPL-2.0-only
95 struct clk *clkin; member
111 st->data[0] = ADMV1013_READ | FIELD_PREP(ADMV1013_REG_ADDR_READ_MSK, reg); in __admv1013_spi_read()
112 st->data[1] = 0x0; in __admv1013_spi_read()
113 st->data[2] = 0x0; in __admv1013_spi_read()
115 t.rx_buf = &st->data[0]; in __admv1013_spi_read()
116 t.tx_buf = &st->data[0]; in __admv1013_spi_read()
119 ret = spi_sync_transfer(st->spi, &t, 1); in __admv1013_spi_read()
123 *val = FIELD_GET(ADMV1013_REG_DATA_MSK, get_unaligned_be24(&st->data[0])); in __admv1013_spi_read()
133 mutex_lock(&st->lock); in admv1013_spi_read()
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H A Dadmv1014.c1 // SPDX-License-Identifier: GPL-2.0-only
117 static const char * const quad_se_mode_names[] = { "se-pos", "se-neg", "diff" };
121 struct clk *clkin; member
142 st->data[0] = ADMV1014_READ | FIELD_PREP(ADMV1014_REG_ADDR_READ_MSK, reg); in __admv1014_spi_read()
143 st->data[1] = 0; in __admv1014_spi_read()
144 st->data[2] = 0; in __admv1014_spi_read()
146 t.rx_buf = &st->data[0]; in __admv1014_spi_read()
147 t.tx_buf = &st->data[0]; in __admv1014_spi_read()
148 t.len = sizeof(st->data); in __admv1014_spi_read()
150 ret = spi_sync_transfer(st->spi, &t, 1); in __admv1014_spi_read()
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/linux/drivers/clk/
H A Dclk-cdce706.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI CDCE706 programmable 3-PLL clock synthesizer driver
11 #include <linux/clk-provider.h>
50 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4))
82 struct cdce706_hw_data clkin[1]; member
115 int rc = regmap_read(dev_data->regmap, reg | 0x80, val); in cdce706_reg_read()
118 dev_err(&dev_data->client->dev, "error reading reg %u", reg); in cdce706_reg_read()
125 int rc = regmap_write(dev_data->regmap, reg | 0x80, val); in cdce706_reg_write()
128 dev_err(&dev_data->client->dev, "error writing reg %u", reg); in cdce706_reg_write()
135 int rc = regmap_update_bits(dev_data->regmap, reg | 0x80, mask, val); in cdce706_reg_update()
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/linux/sound/soc/renesas/rcar/
H A Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
35 struct clk *clkin[CLKINMAX]; member
52 (i < adg->clkin_size) && \
53 ((pos) = adg->clkin[i]); \
57 (i < adg->clkout_size) && \
58 ((pos) = adg->clkout[i]); \
60 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
63 [CLKA] = "clkin",
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