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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,spmi-clkdiv.txt1 Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
3 clkdiv configures the clock frequency of a set of outputs on the PMIC.
14 Definition: must be "qcom,spmi-clkdiv".
19 Definition: base address of CLKDIV peripherals.
24 Definition: number of CLKDIV peripherals.
46 compatible = "qcom,spmi-clkdiv";
H A Dqcom,spmi-clkdiv.yaml4 $id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml#
20 const: qcom,spmi-clkdiv
38 description: Number of CLKDIV peripherals.
57 compatible = "qcom,spmi-clkdiv";
H A Drenesas,emev2-smu.txt21 - compatible: Should be "renesas,emev2-smu-clkdiv"
40 compatible = "renesas,emev2-smu-clkdiv";
87 compatible = "renesas,emev2-smu-clkdiv";
H A Dbaikal,bt1-ccu-div.yaml58 CLKDIV--|--| | | |-|->CLKLOUT
68 accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
72 figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
H A Drenesas,emev2-smu.yaml49 const: renesas,emev2-smu-clkdiv
129 compatible = "renesas,emev2-smu-clkdiv";
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Demev2.dtsi72 compatible = "renesas,emev2-smu-clkdiv";
84 compatible = "renesas,emev2-smu-clkdiv";
103 compatible = "renesas,emev2-smu-clkdiv";
109 compatible = "renesas,emev2-smu-clkdiv";
115 compatible = "renesas,emev2-smu-clkdiv";
121 compatible = "renesas,emev2-smu-clkdiv";
/freebsd/sys/arm/ti/
H A Dti_spi.c121 uint32_t clkdiv, conf, div, extclk, reg; in ti_spi_set_clock() local
123 clkdiv = TI_SPI_GCLK / freq; in ti_spi_set_clock()
124 if (clkdiv > MCSPI_EXTCLK_MSK) { in ti_spi_set_clock()
126 clkdiv = 0; in ti_spi_set_clock()
128 while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) { in ti_spi_set_clock()
129 clkdiv++; in ti_spi_set_clock()
132 conf = clkdiv << MCSPI_CONF_CLK_SHIFT; in ti_spi_set_clock()
134 extclk = clkdiv >> 4; in ti_spi_set_clock()
135 clkdiv &= MCSPI_CONF_CLK_MSK; in ti_spi_set_clock()
136 conf = MCSPI_CONF_CLKG | clkdiv << MCSPI_CONF_CLK_SHIFT; in ti_spi_set_clock()
H A Dti_sdhci.c174 uint32_t clkdiv, val32; in ti_sdhci_read_2() local
191 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & in ti_sdhci_read_2()
194 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; in ti_sdhci_read_2()
196 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & in ti_sdhci_read_2()
281 uint32_t clkdiv, val32; in ti_sdhci_write_2() local
289 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; in ti_sdhci_write_2()
291 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & in ti_sdhci_write_2()
293 clkdiv *= 2; in ti_sdhci_write_2()
294 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) in ti_sdhci_write_2()
295 clkdiv = MMCHS_SYSCTL_CLKD_MASK; in ti_sdhci_write_2()
[all …]
/freebsd/sys/dev/iicbus/controller/rockchip/
H A Drk_i2c.c169 uint32_t clkdiv; in rk_i2c_get_clkdiv() local
176 clkdiv = (sclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1; in rk_i2c_get_clkdiv()
177 clkdiv &= RK_I2C_CLKDIVL_MASK; in rk_i2c_get_clkdiv()
179 clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv; in rk_i2c_get_clkdiv()
181 return (clkdiv); in rk_i2c_get_clkdiv()
188 uint32_t clkdiv; in rk_i2c_reset() local
195 clkdiv = rk_i2c_get_clkdiv(sc, busfreq); in rk_i2c_reset()
200 RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv); in rk_i2c_reset()
/freebsd/sys/arm/ti/am335x/
H A Dam335x_ehrpwm.c242 u_int clkdiv, hspclkdiv, pwmclk, pwmtick, tbprd; in am335x_ehrpwm_cfg_period() local
257 for (clkdiv = 0; clkdiv < 8; ++clkdiv) { in am335x_ehrpwm_cfg_period()
258 const u_int cd = 1 << clkdiv; in am335x_ehrpwm_cfg_period()
289 regval |= TBCTL_CLKDIV(clkdiv) | TBCTL_HSPCLKDIV(hspclkdiv); in am335x_ehrpwm_cfg_period()
293 device_printf(sc->sc_dev, "clkdiv %u hspclkdiv %u tbprd %u " in am335x_ehrpwm_cfg_period()
295 clkdiv, hspclkdiv, tbprd - 1, in am335x_ehrpwm_cfg_period()
/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt49 adi,12bit-clkdiv-mode != 0
51 Valid values for the clkdiv mode are:
H A Dadi,adf4350.yaml116 Clock divider value used when adi,12bit-clkdiv-mode != 0
122 Valid values for the clkdiv mode are:
/freebsd/sys/contrib/device-tree/src/arc/
H A Dabilis_tb10x.dtsi197 output-clkdiv = <4>;
/freebsd/sys/arm/freescale/imx/
H A Dimx_i2c.c112 struct clkdiv { struct
116 static struct clkdiv clkdiv_table[] = { argument
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam43xx-clocks.dtsi693 cpsw_50m_clkdiv: clock-cpsw-50m-clkdiv {
702 cpsw_5m_clkdiv: clock-cpsw-5m-clkdiv {
/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipcreg.h411 /* Fields in clkdiv */
459 #define CHIPC_SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
/freebsd/tools/tools/cxgbtool/
H A Dreg_defs_t3.c1689 { "ClkDiv", 0, 12 },
1702 { "ClkDiv", 5, 8 },
1721 { "ClkDiv", 2, 8 },
H A Dreg_defs_t3b.c1759 { "ClkDiv", 0, 12 },
1772 { "ClkDiv", 5, 8 },
1791 { "ClkDiv", 2, 8 },
H A Dreg_defs_t3c.c2003 { "ClkDiv", 0, 12 },
2016 { "ClkDiv", 5, 8 },
2035 { "ClkDiv", 2, 8 },
/freebsd/sys/arm/ti/cpsw/
H A Dif_cpsw.c658 /* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */ in cpsw_init()
659 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */ in cpsw_init()
/freebsd/sys/dev/cxgb/common/
H A Dcxgb_t3_hw.c250 u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1; in mi1_init() local
251 u32 val = F_PREEN | V_CLKDIV(clkdiv); in mi1_init()
/freebsd/usr.sbin/cxgbetool/
H A Dreg_defs_t4.c30708 { "ClkDiv", 5, 8 },
30730 { "ClkDiv", 0, 12 },
H A Dreg_defs_t6.c38780 { "ClkDiv", 5, 8 },
38802 { "ClkDiv", 0, 12 },
H A Dreg_defs_t5.c40527 { "ClkDiv", 5, 8 },
40549 { "ClkDiv", 0, 12 },