xref: /linux/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma.yaml (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: STMicroelectronics STM32 DMA Controller
8
9description: |
10  The STM32 DMA is a general-purpose direct memory access controller capable of
11  supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12  DMA clients connected to the STM32 DMA controller must use the format
13  described in the dma.txt file, using a four-cell specifier for each
14  channel: a phandle to the DMA controller plus the following four integer cells:
15    1. The channel id
16    2. The request line number
17    3. A 32bit mask specifying the DMA channel configuration which are device
18      dependent:
19        -bit 9: Peripheral Increment Address
20          0x0: no address increment between transfers
21          0x1: increment address between transfers
22        -bit 10: Memory Increment Address
23          0x0: no address increment between transfers
24          0x1: increment address between transfers
25        -bit 15: Peripheral Increment Offset Size
26          0x0: offset size is linked to the peripheral bus width
27          0x1: offset size is fixed to 4 (32-bit alignment)
28        -bit 16-17: Priority level
29          0x0: low
30          0x1: medium
31          0x2: high
32          0x3: very high
33    4. A 32bit bitfield value specifying DMA features which are device dependent:
34       -bit 0-1: DMA FIFO threshold selection
35         0x0: 1/4 full FIFO
36         0x1: 1/2 full FIFO
37         0x2: 3/4 full FIFO
38         0x3: full FIFO
39       -bit 2: DMA direct mode
40         0x0: FIFO mode with threshold selectable with bit 0-1
41         0x1: Direct mode: each DMA request immediately initiates a transfer
42              from/to the memory, FIFO is bypassed.
43       -bit 4: alternative DMA request/acknowledge protocol
44         0x0: Use standard DMA ACK management, where ACK signal is maintained
45              up to the removal of request and transfer completion
46         0x1: Use alternative DMA ACK management, where ACK de-assertion does
47              not wait for the de-assertion of the REQuest, ACK is only managed
48              by transfer completion. This must only be used on channels
49              managing transfers for STM32 USART/UART.
50
51
52maintainers:
53  - Amelie Delaunay <amelie.delaunay@foss.st.com>
54
55allOf:
56  - $ref: /schemas/dma/dma-controller.yaml#
57
58properties:
59  "#dma-cells":
60    const: 4
61
62  compatible:
63    const: st,stm32-dma
64
65  reg:
66    maxItems: 1
67
68  clocks:
69    maxItems: 1
70
71  interrupts:
72    maxItems: 8
73    description: Should contain all of the per-channel DMA
74      interrupts in ascending order with respect to the
75      DMA channel index.
76
77  resets:
78    maxItems: 1
79
80  st,mem2mem:
81    $ref: /schemas/types.yaml#/definitions/flag
82    description: if defined, it indicates that the controller
83      supports memory-to-memory transfer
84
85  access-controllers:
86    minItems: 1
87    maxItems: 2
88
89required:
90  - compatible
91  - reg
92  - clocks
93  - interrupts
94
95unevaluatedProperties: false
96
97examples:
98  - |
99    #include <dt-bindings/interrupt-controller/arm-gic.h>
100    #include <dt-bindings/clock/stm32mp1-clks.h>
101    #include <dt-bindings/reset/stm32mp1-resets.h>
102    dma-controller@40026400 {
103      compatible = "st,stm32-dma";
104      reg = <0x40026400 0x400>;
105      interrupts = <56>,
106                   <57>,
107                   <58>,
108                   <59>,
109                   <60>,
110                   <68>,
111                   <69>,
112                   <70>;
113      clocks = <&clk_hclk>;
114      #dma-cells = <4>;
115      st,mem2mem;
116      resets = <&rcc 150>;
117      dma-requests = <8>;
118    };
119
120...
121