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/linux/drivers/clk/keystone/
H A Dsci-clk.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
6 * Tero Kristo <t-kristo@ti.com>
8 #include <linux/clk-provider.h>
24 * struct sci_clk_provider - TI SCI clock provider representation
27 * @dev: Device pointer for the clock provider
29 * @num_clocks: Total number of clocks for this provider
40 * struct sci_clk - TI SCI clock representation
45 * @provider: Master clock provider
56 struct sci_clk_provider *provider; member
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/linux/drivers/interconnect/
H A Dicc-clk.c1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <linux/clk.h>
8 #include <linux/interconnect-clk.h>
9 #include <linux/interconnect-provider.h>
12 struct clk *clk; member
17 struct icc_provider provider; member
23 container_of(_provider, struct icc_clk_provider, provider)
27 struct icc_clk_node *qn = src->data; in icc_clk_set()
30 if (!qn || !qn->clk) in icc_clk_set()
33 if (!src->peak_bw) { in icc_clk_set()
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/linux/drivers/clk/tegra/
H A Dclk-tegra210-emc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
35 struct tegra210_clk_emc_provider *provider; member
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
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/linux/drivers/clk/ti/
H A Dclkctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
14 #include <linux/clk/ti.h>
50 struct clk_hw *clk; member
94 * one is during suspend-resume cycle while timekeeping is in _omap4_is_timeout()
103 if (time->cycles++ < timeout) { in _omap4_is_timeout()
108 if (!ktime_to_ns(time->start)) { in _omap4_is_timeout()
109 time->start = ktime_get(); in _omap4_is_timeout()
113 if (ktime_us_delta(ktime_get(), time->start) < timeout) { in _omap4_is_timeout()
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H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-kristo@ti.com>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
14 #include <linux/clk/t
175 struct clk *clk; ti_dt_clocks_register() local
519 struct clk *clk; ti_clk_add_aliases() local
587 ti_clk_add_alias(struct clk * clk,const char * con) ti_clk_add_alias() argument
622 struct clk *clk; of_ti_clk_register() local
653 struct clk *clk; of_ti_clk_register_omap_hw() local
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/linux/drivers/memory/tegra/
H A Dtegra186-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
24 struct clk *clk; member
35 struct icc_provider provider; member
42 * to control the EMC frequency. The top-level directory can be found here:
48 * - available_rates: This file contains a list of valid, space-separated
51 * - min_rate: Writing a value to this file sets the given frequency as the
56 * - max_rate: Similarily to the min_rate file, writing a value to this file
68 for (i = 0; i < emc->num_dvfs; i++) in tegra186_emc_validate_rate()
69 if (rate == emc->dvfs[i].rate) in tegra186_emc_validate_rate()
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H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
10 #include <linux/clk.h>
12 #include <linux/clk/tegra.h>
15 #include <linux/interconnect-provider.h>
488 struct clk *clk; member
504 struct icc_provider provider; member
512 /* protect shared rate-change code path */
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
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H A Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
13 #include <linux/clk.h>
14 #include <linux/clk/tegra.h>
18 #include <linux/interconnect-provider.h>
358 struct icc_provider provider; member
360 struct clk *clk; member
392 /* protect shared rate-change code path */
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/linux/drivers/clk/qcom/
H A Dclk-cbf-8996.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/interconnect-clk.h>
9 #include <linux/interconnect-provider.h>
15 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
17 #include "clk-alpha-pll.h"
18 #include "clk-regmap.h"
112 regmap_read(clkr->regmap, mux->reg, &val); in clk_cbf_8996_mux_get_parent()
125 return regmap_update_bits(clkr->regmap, mux->reg, CBF_MUX_PARENT_MASK, val); in clk_cbf_8996_mux_set_parent()
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/linux/drivers/phy/nuvoton/
H A Dphy-ma35d1-usb2.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
19 #define PHY0POR BIT(0) /* PHY Power-On Reset Control Bit */
21 #define PHY0COMN BIT(2) /* PHY Common Block Power-Down Control */
25 struct clk *clk; member
36 ret = clk_prepare_enable(p_phy->clk); in ma35_usb_phy_power_on()
38 dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret); in ma35_usb_phy_power_on()
42 regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val); in ma35_usb_phy_power_on()
48 ret = regmap_read_poll_timeout(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, val, in ma35_usb_phy_power_on()
58 regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, (PHY0POR | PHY0SUSPEND)); in ma35_usb_phy_power_on()
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/linux/Documentation/devicetree/bindings/sound/
H A Dmt8195-mt6359.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195-mt6359.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Trevor Wu <trevor.wu@mediatek.com>
16 - $ref: sound-card-common.yaml#
21 - mediatek,mt8195_mt6359_rt1019_rt5682
22 - mediatek,mt8195_mt6359_rt1011_rt5682
23 - mediatek,mt8195_mt6359_max98390_rt5682
29 audio-routing:
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H A Dmt8192-mt6359-rt1015-rt5682.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8192-mt6359-rt1015-rt5682.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxin Yu <jiaxin.yu@mediatek.com>
11 - Shane Chien <shane.chien@mediatek.com>
17 - $ref: sound-card-common.yaml#
22 - mediatek,mt8192_mt6359_rt1015_rt5682
23 - mediatek,mt8192_mt6359_rt1015p_rt5682
24 - mediatek,mt8192_mt6359_rt1015p_rt5682s
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H A Dmt8186-mt6366-rt1019-rt5682s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8186-mt6366-rt1019-rt5682s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxin Yu <jiaxin.yu@mediatek.com>
16 - $ref: sound-card-common.yaml#
21 - mediatek,mt8186-mt6366-rt1019-rt5682s-sound
22 - mediatek,mt8186-mt6366-rt5682s-max98360-sound
23 - mediatek,mt8186-mt6366-rt5650-sound
25 audio-routing:
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H A Dmt8186-mt6366-da7219-max98357.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8186-mt6366-da7219-max98357.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxin Yu <jiaxin.yu@mediatek.com>
16 - $ref: sound-card-common.yaml#
21 - mediatek,mt8186-mt6366-da7219-max98357-sound
23 audio-routing:
24 $ref: /schemas/types.yaml#/definitions/non-unique-string-array
35 - HDMI1
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/linux/drivers/clk/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
100 #include <trace/events/clk.h>
102 struct clk { struct
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H A Dclk_kunit_helpers.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit helpers for clk providers and consumers
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
11 #include <kunit/clk.h>
15 clk_disable_unprepare, struct clk *);
17 * clk_prepare_enable_kunit() - Test managed clk_prepare_enable()
19 * @clk: clk to prepare and enable
23 int clk_prepare_enable_kunit(struct kunit *test, struct clk *clk) in clk_prepare_enable_kunit() argument
27 ret = clk_prepare_enable(clk); in clk_prepare_enable_kunit()
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H A Dclk-fixed-mmio.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/clk-provider.h>
20 struct clk_hw *clk; in fixed_mmio_clk_setup() local
21 const char *clk_name = node->name; in fixed_mmio_clk_setup()
29 return ERR_PTR(-EIO); in fixed_mmio_clk_setup()
34 of_property_read_string(node, "clock-output-names", &clk_name); in fixed_mmio_clk_setup()
36 clk = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0, freq); in fixed_mmio_clk_setup()
37 if (IS_ERR(clk)) { in fixed_mmio_clk_setup()
39 return clk; in fixed_mmio_clk_setup()
42 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, clk); in fixed_mmio_clk_setup()
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/linux/drivers/interconnect/qcom/
H A Dicc-rpm.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <linux/soc/qcom/smd-rpm.h>
11 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
12 #include <linux/clk.h>
13 #include <linux/interconnect-provider.h>
20 container_of(_provider, struct qcom_icc_provider, provider)
29 * struct rpm_clk_resource - RPM bus clock resource
41 * struct qcom_icc_provider - Qualcomm specific interconnect provider
42 * @provider: generic interconnect provider
44 * @type: the ICC provider type
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/linux/drivers/clk/mediatek/
H A Dclk-mt7629-eth.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include "clk-mtk.h"
13 #include "clk-gate.h"
15 #include <dt-bindings/clock/mt7629-clk.h>
76 struct device_node *node = pdev->dev.of_node; in clk_mt7629_ethsys_init()
81 return -ENOMEM; in clk_mt7629_ethsys_init()
83 mtk_clk_register_gates(&pdev->dev, node, eth_clks, in clk_mt7629_ethsys_init()
88 dev_err(&pdev->dev, in clk_mt7629_ethsys_init()
89 "could not register clock provider: %s: %d\n", in clk_mt7629_ethsys_init()
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/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,sdx75-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sdx75-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SDX75
10 - Rohit Agarwal <quic_rohiagar@quicinc.com>
14 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16 associated with each execution environment. Provider nodes must point to at
17 least one RPMh device child node pertaining to their RSC and each provider
23 - qcom,sdx75-clk-virt
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H A Dqcom,qdu1000-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,qdu1000-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on QDU1000
10 - Georgi Djakov <djakov@kernel.org>
11 - Odelu Kukatla <quic_okukatla@quicinc.com>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
17 associated with each execution environment. Provider nodes must point to at
18 least one RPMh device child node pertaining to their RSC and each provider
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H A Dqcom,x1e80100-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,x1e80100-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on X1E80100
10 - Rajendra Nayak <quic_rjendra@quicinc.com>
11 - Abel Vesa <abel.vesa@linaro.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
17 associated with each execution environment. Provider nodes must point to at
18 least one RPMh device child node pertaining to their RSC and each provider
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/linux/drivers/phy/renesas/
H A Dphy-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car Gen2 PHY driver
10 #include <linux/clk.h>
64 struct clk *clk; member
79 struct rcar_gen2_channel *channel = phy->channel; in rcar_gen2_phy_init()
80 struct rcar_gen2_phy_driver *drv = channel->drv; in rcar_gen2_phy_init()
88 * driver. Achieving this with cmpxcgh() should be SMP-safe. in rcar_gen2_phy_init()
90 if (cmpxchg(&channel->selected_phy, -1, phy->number) != -1) in rcar_gen2_phy_init()
91 return -EBUSY; in rcar_gen2_phy_init()
93 clk_prepare_enable(drv->clk); in rcar_gen2_phy_init()
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/linux/drivers/clk/sunxi/
H A Dclk-sun4i-pll3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup()
28 struct clk *clk; in sun4i_a10_pll3_setup() local
31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
44 gate->reg = reg; in sun4i_a10_pll3_setup()
45 gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT; in sun4i_a10_pll3_setup()
46 gate->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
52 mult->reg = reg; in sun4i_a10_pll3_setup()
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/linux/drivers/clk/rockchip/
H A Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
12 #include "clk.h"
40 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
57 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
87 * provider of MMC host. However, things may go wrong if in rockchip_mmc_set_phase()
96 pr_err("%s: invalid clk rate\n", __func__); in rockchip_mmc_set_phase()
97 return -EINVAL; in rockchip_mmc_set_phase()
105 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
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