Lines Matching +full:clk +full:- +full:provider

1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
13 #include "clk.h"
43  * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
60 	if (mmc_clock->grf)
61 		regmap_read(mmc_clock->grf, mmc_clock->grf_reg, &raw_value);
63 		raw_value = readl(mmc_clock->reg);
65 	raw_value >>= mmc_clock->shift;
95 	 * provider of MMC host. However, things may go wrong if
104 		pr_err("%s: invalid clk rate\n", __func__);
105 		return -EINVAL;
113 	 * actually go non-monotonic.  We don't go _too_ monotonic
132 	 * don't overflow 32-bit / 64-bit numbers.
145 	raw_value = HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift);
147 	if (mmc_clock->grf)
148 		regmap_write(mmc_clock->grf, mmc_clock->grf_reg, raw_value);
150 		writel(raw_value, mmc_clock->reg);
152 	pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
154 		mmc_clock->reg, raw_value>>(mmc_clock->shift),
182 	 * clock provider be reparented from orphan to its real parent in the
186 	 * set the max-frequency to match the boards' ability but we can't go
189 	if (ndata->old_rate <= ndata->new_rate)
193 		mmc_clock->cached_phase =
194 			rockchip_mmc_get_phase(&mmc_clock->hw);
195 	else if (mmc_clock->cached_phase != -EINVAL &&
197 		rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase);
202 struct clk *rockchip_clk_register_mmc(const char *name,
210 	struct clk *clk;
215 		return ERR_PTR(-ENOMEM);
223 	mmc_clock->hw.init = &init;
224 	mmc_clock->reg = reg;
225 	mmc_clock->grf = grf;
226 	mmc_clock->grf_reg = grf_reg;
227 	mmc_clock->shift = shift;
229 	clk = clk_register(NULL, &mmc_clock->hw);
230 	if (IS_ERR(clk)) {
231 		ret = PTR_ERR(clk);
235 	mmc_clock->clk_rate_change_nb.notifier_call =
237 	ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb);
241 	return clk;
243 	clk_unregister(clk);