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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dmt8195-mt6359.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195-mt6359.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Trevor Wu <trevor.wu@mediatek.com>
16 - $ref: sound-card-common.yaml#
21 - mediatek,mt8195_mt6359_rt1019_rt5682
22 - mediatek,mt8195_mt6359_rt1011_rt5682
23 - mediatek,mt8195_mt6359_max98390_rt5682
29 audio-routing:
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H A Dmt8186-mt6366-rt1019-rt5682s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8186-mt6366-rt1019-rt5682s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxin Yu <jiaxin.yu@mediatek.com>
16 - $ref: sound-card-common.yaml#
21 - mediatek,mt8186-mt6366-rt1019-rt5682s-sound
22 - mediatek,mt8186-mt6366-rt5682s-max98360-sound
23 - mediatek,mt8186-mt6366-rt5650-sound
25 audio-routing:
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H A Dmt8192-mt6359-rt1015-rt5682.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8192-mt6359-rt1015-rt5682.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxin Yu <jiaxin.yu@mediatek.com>
11 - Shane Chien <shane.chien@mediatek.com>
17 - $ref: sound-card-common.yaml#
22 - mediatek,mt8192_mt6359_rt1015_rt5682
23 - mediatek,mt8192_mt6359_rt1015p_rt5682
24 - mediatek,mt8192_mt6359_rt1015p_rt5682s
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H A Dmt8186-mt6366-da7219-max98357.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8186-mt6366-da7219-max98357.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxin Yu <jiaxin.yu@mediatek.com>
16 - $ref: sound-card-common.yaml#
21 - mediatek,mt8186-mt6366-da7219-max98357-sound
23 audio-routing:
24 $ref: /schemas/types.yaml#/definitions/non-unique-string-array
35 - HDMI1
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H A Dmediatek,mt8188-mt6359.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt8188-mt635
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H A Dfsl,mqs.txt4 - compatible : Must contain one of "fsl,imx6sx-mqs", "fsl,codec-mqs"
5 "fsl,imx8qm-mqs", "fsl,imx8qxp-mqs", "fsl,imx93-mqs".
6 - clocks : A list of phandles + clock-specifiers, one for each entry in
7 clock-names
8 - clock-names : "mclk" - must required.
9 "core" - required if compatible is "fsl,imx8qm-mqs", it
11 - gpr : A phandle of General Purpose Registers in IOMUX Controller.
12 Required if compatible is "fsl,imx6sx-mqs".
14 Required if compatible is "fsl,imx8qm-mqs":
15 - power-domains: A phandle of PM domain provider node.
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/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dqcom,qdu1000-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,qdu1000-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on QDU1000
10 - Georgi Djakov <djakov@kernel.org>
11 - Odelu Kukatla <quic_okukatla@quicinc.com>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
17 associated with each execution environment. Provider nodes must point to at
18 least one RPMh device child node pertaining to their RSC and each provider
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H A Dqcom,sm8550-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550
10 - Abel Vesa <abel.vesa@linaro.org>
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
17 associated with each execution environment. Provider nodes must point to at
18 least one RPMh device child node pertaining to their RSC and each provider
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H A Dfsl,imx8m-noc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
27 - items:
28 - enum:
29 - fsl,imx8mm-nic
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H A Dqcom,sm6350-rpmh.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,sm6350-rpmh.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6350 RPMh Network-On-Chip Interconnect
10 - Luca Weiss <luca.weiss@fairphone.com>
13 Qualcomm RPMh-based interconnect provider on SM6350.
16 - $ref: qcom,rpmh-common.yaml#
21 - qcom,sm6350-aggre1-noc
22 - qcom,sm6350-aggre2-noc
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk
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H A Dxlnx,zynqmp-clk.txt1 --------------------------------------------------------------------------
4 --------------------------------------------------------------------------
7 as clock provider for all clock consumers of PS clocks.
12 - #clock-cells: Must be 1
13 - compatible: Must contain: "xlnx,zynqmp-clk"
14 - clocks: List of clock specifiers which are external input
18 - clock-names: List of clock names which are exteral input clocks
26 - pss_ref_clk (PS reference clock)
27 - video_clk (reference clock for video system )
28 - pss_alt_ref_clk (alternative PS reference clock)
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H A Dzynq-7000.txt3 The Zynq EPP has several different clk providers, each with there own bindings.
11 required input clock frequencies from the devicetree and acts as clock provider
15 - #clock-cells : Must be 1
16 - compatible : "xlnx,ps7-clkc"
17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
18 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
20 - clock-output-names : List of strings used to name the clock outputs. Shall be
24 - clocks : as described in the clock bindings
25 - clock-names : as described in the clock bindings
26 - fclk-enable : Bit mask to enable FCLKs statically at boot time.
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H A Dmediatek,mt7621-sysc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
21 [1]: <include/dt-bindings/clock/mt7621-clk.h>.
25 This node is also a reset provider for all the peripherals.
28 [2]: <include/dt-bindings/reset/mt7621-reset.h>.
33 - const: mediatek,mt7621-sysc
34 - const: syscon
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H A Dmicrochip,sparx5-dpll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
18 const: microchip,sparx5-dpll
26 '#clock-cells':
30 - compatible
31 - reg
32 - clocks
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/freebsd/sys/contrib/device-tree/Bindings/power/
H A Dpower_domain.txt8 their PM domains provided by PM domain providers. A PM domain provider can be
10 domains. A consumer node can refer to the provider by a phandle and a set of
12 #power-domain-cells property in the PM domain provider node.
16 See power-domain.yaml.
21 - power-domains : A list of PM domain specifiers, as defined by bindings of
22 the power controller that is the PM domain provider.
25 - power-domain-names : A list of power domain name strings sorted in the same
26 order as the power-domains property. Consumers drivers will use
27 power-domain-names to match power domains with power-domains
32 leaky-device@12350000 {
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/freebsd/sys/dev/clk/rockchip/
H A Drk_cru.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dev/clk/clk.h>
48 #include <dev/clk/clk_gate.h>
49 #include <dev/clk/clk_fixed.h>
50 #include <dev/clk/clk_link.h>
53 #include <dev/clk/rockchip/rk_clk_composite.h>
54 #include <dev/clk/rockchip/rk_clk_gate.h>
55 #include <dev/clk/rockchip/rk_clk_mux.h>
56 #include <dev/clk/rockchip/rk_clk_pll.h>
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8186-corsola.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
7 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/regulator/mediatek,mt6397-regulator.h>
26 stdout-path = "serial0:115200n8";
35 backlight_lcd0: backlight-lcd0 {
36 compatible = "pwm-backlight";
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H A Dmt8195-cherry.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h>
25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>;
28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023>;
32 power-supply = <&ppvar_sys>;
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/freebsd/sys/arm/conf/
H A Dstd.qca7 makeoptions CONF_CFLAGS="-march=armv7a"
16 device clk
45 # PSCI - SMC calls, needed for qualcomm SCM
48 # Clock/Reset provider
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-davinci.txt7 - compatible: "ti,davinci-i2c" or "ti,keystone-i2c";
8 - reg : Offset and length of the register set for the device
9 - clocks: I2C functional clock phandle.
11 Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
13 SoC-specific Required Properties:
17 - power-domains: Should contain a phandle to a PM domain provider node
20 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
23 - interrupts : standard interrupt property.
24 - clock-frequency : desired I2C bus clock frequency in Hz.
25 - ti,has-pfunc: boolean; if defined, it indicates that SoC supports PFUNC
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/freebsd/sys/dev/clk/allwinner/
H A Daw_ccung.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dev/clk/clk.h>
48 #include <dev/clk/clk_gate.h>
52 #include <dev/clk/allwinner/aw_ccung.h>
53 #include <dev/clk/allwinner/aw_clk.h>
70 { -1, 0 }
73 #define CCU_READ4(sc, reg) bus_read_4((sc)->res, (reg))
74 #define CCU_WRITE4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
125 if (id >= sc->nresets || sc->resets[id].offset == 0) in aw_ccung_reset_assert()
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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-davinci.txt4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
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/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dc_can.txt2 -------------------------------------------------
5 - compatible : Should be "bosch,c_can" for C_CAN controllers and
7 Can be "ti,dra7-d_can", "ti,am3352-d_can" or
8 "ti,am4372-d_can".
9 - reg : physical base address and size of the C_CAN/D_CAN
11 - interrupts : property with a value describing the interrupt
15 - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the
19 - power-domains : Should contain a phandle to a PM domain provider node
22 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
23 - clocks : CAN functional clock phandle. This property is as per the
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/freebsd/sys/contrib/device-tree/Bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware
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