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/linux/drivers/cpufreq/
H A Ds3c64xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/clk.h>
56 unsigned int new_freq = s3c64xx_freq_table[index].frequency; in s3c64xx_cpufreq_set_target()
63 old_freq = clk_get_rate(policy->clk) / 1000; in s3c64xx_cpufreq_set_target()
68 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
69 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
78 ret = clk_set_rate(policy->clk, new_freq * 1000); in s3c64xx_cpufreq_set_target()
88 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
89 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
93 if (clk_set_rate(policy->clk, old_freq * 1000) < 0) in s3c64xx_cpufreq_set_target()
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/linux/Documentation/devicetree/bindings/net/
H A Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
19 - if:
24 - ethernet-phy-id004d.d0c0
33 - description:
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H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgm20b.c19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 #include <subdev/clk.h>
89 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
90 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-1 */
99 .coeff_slope = -165230,
136 /* safe frequency we can use at minimum voltage */
160 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) in gm20b_pllg_read_mnp() argument
162 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_pllg_read_mnp()
163 struct nvkm_device *device = subdev->device; in gm20b_pllg_read_mnp()
166 gk20a_pllg_read_mnp(&clk->base, &pll->base); in gm20b_pllg_read_mnp()
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/linux/drivers/sh/clk/
H A Dcore.c4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
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/linux/rust/kernel/
H A Dclk.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! C header: [`include/linux/clk.h`](srctree/include/linux/clk.h)
7 //! Reference: <https://docs.kernel.org/driver-api/clk.html>
11 /// The frequency unit.
13 /// Represents a frequency in hertz, wrapping a [`c_ulong`] value.
18 /// use kernel::clk::Hertz;
38 pub const fn from_khz(khz: c_ulong) -> Self { in from_khz()
43 pub const fn from_mhz(mhz: c_ulong) -> Self { in from_mhz()
48 pub const fn from_ghz(ghz: c_ulong) -> Self { in from_ghz()
52 /// Get the frequency in hertz
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/linux/drivers/i2c/busses/
H A Di2c-digicolor.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
50 struct clk *clk; member
51 unsigned int frequency; member
73 writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND); in dc_i2c_cmd()
78 u8 addr = (msg->addr & 0x7f) << 1; in dc_i2c_addr_cmd()
80 if (msg->flags & I2C_M_RD) in dc_i2c_addr_cmd()
88 writeb_relaxed(data, i2c->regs + II_DATA); in dc_i2c_data()
99 dc_i2c_write_byte(i2c, i2c->msg->buf[i2c->msgbuf_ptr++]); in dc_i2c_write_buf()
104 bool last = (i2c->msgbuf_ptr + 1 == i2c->msg->len); in dc_i2c_next_read()
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/linux/drivers/clocksource/
H A Dmps2-timer.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
51 writel_relaxed(val, to_mps2_clkevt(c)->reg + offset); in clockevent_mps2_writel()
72 u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; in mps2_timer_set_periodic()
84 u32 status = readl_relaxed(ce->reg + TIMER_INT); in mps2_timer_interrupt()
91 writel_relaxed(1, ce->reg + TIMER_INT); in mps2_timer_interrupt()
93 ce->clkevt.event_handler(&ce->clkevt); in mps2_timer_interrupt()
101 struct clk *clk = NULL; in mps2_clockevent_init() local
105 const char *name = "mps2-clkevt"; in mps2_clockevent_init()
107 ret = of_property_read_u32(np, "clock-frequency", &rate); in mps2_clockevent_init()
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H A Darm_arch_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include <linux/arm-smccc.h>
47 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
50 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
51 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
78 * 2) a roll-over time of not less than 40 years
87 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64); in arch_counter_get_width()
180 _retries--; \
216 _retries--; \
217 } while (unlikely((_new - _old) >> 5) && _retries); \
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/linux/sound/soc/renesas/rcar/
H A Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
34 struct clk *adg;
35 struct clk *clkin[CLKINMAX];
36 struct clk *clkout[CLKOUTMAX];
37 struct clk *null_clk;
52 (i < adg->clkin_size) && \
53 ((pos) = adg->clkin[i]); \
57 (i < adg->clkout_size) && \
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/linux/drivers/pwm/
H A Dpwm-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/clk.h>
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
56 struct clk *clk; member
63 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
65 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
72 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
74 writel_relaxed(value, p->base + offset); in brcmstb_pwm_writel()
83 * Fv is derived from the variable frequency output. The variable frequency
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/linux/drivers/clk/pxa/
H A Dclk-pxa25x.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
12 #include <linux/clk-provider.h>
13 #include <linux/clk.h>
14 #include <linux/clk/pxa.h>
21 #include <dt-bindings/clock/pxa-clock.h>
22 #include "clk-pxa.h"
23 #include "clk-pxa2xx.h"
46 /* Crystal Frequency to Memory Frequency Multiplier (L) */
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/linux/drivers/clk/at91/
H A Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/clk/at91_pmc.h>
33 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
53 "atmel,sama5d2-clk-audio-pll-frac",
59 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
79 "atmel,sama5d2-clk-audio-pll-pad",
85 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
105 "atmel,sama5d2-clk-audio-pll-pmc",
161 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
[all …]
/linux/drivers/clk/
H A Dclk-max9485.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk.h>
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/maxim,max9485.h>
35 unsigned long out; member
40 * Ordered by frequency. For frequency the hardware can generate with
78 struct clk *xclk;
96 drvdata->reg_value &= ~mask; in max9485_update_bits()
97 drvdata->reg_value |= value; in max9485_update_bits()
99 dev_dbg(&drvdata->client->dev, in max9485_update_bits()
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_4_ppsmc.h19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
27 /*! @mainpage PMFW-PPS (PPLib) Message Interface
62 …MC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
72 #define PPSMC_MSG_SetHardMinSocclkByFreq 0x13 ///< Set hard min for SOC CLK
78 #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
79 #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
82 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
83 #define PPSMC_MSG_SetHardMinGfxClk 0x1C ///< Set hard min for GFX CLK
85 #define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x1D ///< Set soft max for SOC CLK
93 #define PPSMC_MSG_SetSoftMinSocclkByFreq 0x24 ///< Set soft min for SOC CLK
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-hummingboard-pulse.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
6 /dts-v1/;
8 #include "dt-bindings/usb/pd.h"
9 #include "imx8mq-sr-som.dtsi"
13 compatible = "solidrun,hummingboard-pulse", "fsl,imx8mq";
16 stdout-path = &uart1;
19 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
20 compatible = "regulator-fixed";
21 pinctrl-names = "default";
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/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
91 struct clk *tegra_clk_register_sync_source(const char *name,
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
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/linux/drivers/hwmon/
H A Dg762.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * g762 - Driver for the Global Mixed-mode Technology Inc. fan speed
15 * http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf
27 * http://www.gmt.com.tw/product/datasheet/EDS-762_3.pdf
36 #include <linux/hwmon-sysfs.h>
40 #include <linux/clk.h>
66 #define G762_REG_FAN_CMD1_OUT_MODE 0x20 /* out mode: PWM or DC */
67 #define G762_REG_FAN_CMD1_FAN_MODE 0x10 /* fan mode: closed/open-loop */
80 #define G762_REG_FAN_STA_OOC 0x01 /* fan out of control */
121 struct clk *clk; member
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/linux/arch/arm64/boot/dts/sprd/
H A Dums512.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
51 compatible = "arm,cortex-a55";
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/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12a-radxa-zero.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-g12a.dtsi"
9 #include <dt-bindings/gpio/meson-g12a-gpio.h>
10 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
21 stdout-path = "serial0:115200n8";
29 cvbs-connector {
31 compatible = "composite-video-connector";
35 remote-endpoint = <&cvbs_vdac_out>;
40 hdmi-connector {
[all …]
H A Dmeson-khadas-vim3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/gpio/meson-g12a-gpio.h>
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
22 stdout-path = "serial0:115200n8";
30 adc-keys {
31 compatible = "adc-keys";
32 io-channels = <&saradc 2>;
33 io-channel-names = "buttons";
[all …]
H A Dmeson-g12a-sei510.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-g12a.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/meson-g12a-gpio.h>
12 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
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H A Dmeson-g12a-x96-max.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-g12a.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-g12a-gpio.h>
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
14 compatible = "amediatech,x96-max", "amlogic,g12a";
22 spdif_dit: audio-codec-1 {
23 #sound-dai-cells = <0>;
24 compatible = "linux,spdif-dit";
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/linux/drivers/devfreq/
H A Dimx8m-ddrc.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/arm-smccc.h>
40 * +----------+ |\ +------+
41 * | dram_pll |-------|M| dram_core | |
42 * +----------+ |U|---------->| D |
43 * /--|X| | D |
46 * +---------+ | |
48 * +---------+ | |
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/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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