Lines Matching +full:clk +full:- +full:out +full:- +full:frequency
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
91 struct clk *tegra_clk_register_sync_source(const char *name,
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
112 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
134 struct clk *tegra_clk_register_divider(const char *name,
138 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
146 * (1) Input frequency range (REF).
147 * (2) Comparison frequency range (CF). CF = REF/DIVM.
148 * (3) VCO frequency range (VCO). VCO = CF * DIVN.
150 * The final PLL output frequency (FO) = VCO >> DIVP.
154 * struct tegra_clk_pll_freq_table - PLL frequecy table
175 * struct pdiv_map - map post divider to hw value
186 * struct div_nmp - offset and width of m,n and p fields
215 * struct tegra_clk_pll_params - PLL parameters
217 * @input_min: Minimum input frequency
218 * @input_max: Maximum input frequency
219 * @cf_min: Minimum comparison frequency
220 * @cf_max: Maximum comparison frequency
221 * @vco_min: Minimum VCO frequency
222 * @vco_max: Maximum VCO frequency
257 * @calc_rate: Callback used to change how out of table
275 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
277 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
278 * to be programmed to change output frequency of the PLL.
279 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
280 * to be programmed to change output frequency of the PLL.
281 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
282 * to be programmed to change output frequency of the PLL.
283 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
285 * TEGRA_PLLM - PLLM has additional override settings in PMC. This
287 * TEGRA_PLL_FIXED - We are not supposed to change output frequency
289 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
290 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
292 * TEGRA_PLL_BYPASS - PLL has bypass bit
293 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
294 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
296 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
298 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
369 * struct tegra_clk_pll - Tegra PLL clock
371 * @hw: handle between common and hardware-specifix interfaces
388 * struct tegra_audio_clk_info - Tegra Audio Clk Information
404 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
409 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
414 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
420 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
426 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
432 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
438 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
444 struct clk *tegra_clk_register_plle_tegra114(const char *name,
450 struct clk *tegra_clk_register_plle_tegra210(const char *name,
456 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
462 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
468 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
473 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
479 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
484 struct clk *tegra_clk_register_pllu_tegra114(const char *name,
490 struct clk *tegra_clk_register_pllu_tegra210(const char *name,
497 * struct tegra_clk_pll_out - PLL divider down clock
499 * @hw: handle between common and hardware-specific interfaces
504 * @flags: hardware-specific flags
518 struct clk *tegra_clk_register_pll_out(const char *name,
524 * struct tegra_clk_periph_regs - Registers controlling peripheral clock
543 * struct tegra_clk_periph_gate - peripheral gate clock
546 * @hw: handle between common and hardware-specific interfaces
549 * @flags: hardware-specific flags
554 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
556 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
559 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
583 struct clk *tegra_clk_register_periph_gate(const char *name,
596 struct clk *tegra_clk_register_periph_fixed(const char *name,
605 * struct clk-periph - peripheral clock
608 * @hw: handle between common and hardware-specific interfaces
632 struct clk *tegra_clk_register_periph(const char *name,
636 struct clk *tegra_clk_register_periph_nodiv(const char *name,
710 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
715 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
719 * struct clk_super_mux - super clock
721 * @hw: handle between common and hardware-specific interfaces
724 * @flags: hardware-specific flags
725 * @div2_index: bit controlling divide-by-2
730 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
732 * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5
735 * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super
736 * clocks, it only has a clock-skipper.
757 struct clk *tegra_clk_register_super_mux(const char *name,
761 struct clk *tegra_clk_register_super_clk(const char *name,
765 struct clk *tegra_clk_register_super_cclk(const char *name,
773 * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
775 * @hw: handle between common and hardware-specific interfaces
777 * @flags: hardware-specific flags
793 struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
798 * struct clk_init_table - clock initialization table
812 * struct clk_duplicate - duplicate clocks
845 struct clk *clks[], int clk_max);
848 struct clk *clks[], int clk_max);
851 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
853 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
880 struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np,
884 static inline struct clk *
922 struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter);
924 struct clk *tegra210_clk_register_emc(struct device_node *np,
927 struct clk *tegra_clk_dev_register(struct clk_hw *hw);