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Searched +full:clk +full:- +full:delay +full:- +full:cycles (Results 1 – 25 of 144) sorted by relevance

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/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
28 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
104 u32 clk; member
105 u32 t_bacc; /* burst access valid clock to output delay */
106 u32 t_ces; /* CS setup time to clk */
107 u32 t_avds; /* ADV setup time to clk */
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/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: marvell,armada-380-sdhci
23 reg-names:
26 - reg-names
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/linux/drivers/watchdog/
H A Drenesas_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 * Copyright (C) 2015-17 Renesas Electronics Corporation
9 #include <linux/clk.h>
10 #include <linux/delay.h>
37 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
39 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
40 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
54 struct clk *clk; member
64 writel_relaxed(val, priv->base + reg); in rwdt_write()
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H A Dimgpdc_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * -----
12 * The timeout value is rounded to the next power of two clock cycles.
16 * timeout = 2^(delay + 1) clock cycles
18 * Where 'delay' is the value written in PDC_WDT_CONFIG register.
21 * as a power of two number of watchdog clock cycles. The current implementation
25 * The following table shows how the user-configured timeout relates
29 * -----------------------------------
40 #include <linux/clk.h>
84 struct clk *wdt_clk;
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H A Drzg2l_wdt.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk.h>
9 #include <linux/delay.h>
56 unsigned long delay; member
57 struct clk *pclk;
58 struct clk *osc_clk;
64 /* delay timer when change the setting register */ in rzg2l_wdt_wait_delay()
65 ndelay(priv->delay); in rzg2l_wdt_wait_delay()
80 writel_relaxed(val, priv->base + reg); in rzg2l_wdt_write()
94 time_out = (wdev->timeout * (MICRO / 2)) / in rzg2l_wdt_init_timeout()
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/linux/drivers/memory/
H A Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
13 #include <linux/clk.h>
53 struct clk *clk; member
61 int cycles; in pl172_timing_prop() local
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
66 if (cycles < 0) { in pl172_timing_prop()
67 cycles = 0; in pl172_timing_prop()
68 } else if (cycles > max) { in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
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/linux/drivers/clk/imx/
H A Dclk-lpcg-scu.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
16 #include "clk-scu.h"
25 * struct clk_lpcg_scu - Description of LPCG clock
46 /* e10858 -LPCG clock gating register synchronization errata */
54 * through the interconnect is longer than the minimum delay in lpcg_e10858_writel()
55 * of 4 clock cycles required by the errata. in lpcg_e10858_writel()
56 * Adding a readl will provide sufficient delay to prevent in lpcg_e10858_writel()
57 * back-to-back writes. in lpcg_e10858_writel()
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/linux/drivers/pwm/
H A Dpwm-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
22 #include <linux/clk.h>
23 #include <linux/delay.h>
80 struct clk *clk; member
87 * pending we delay disabling the PWM until the new configuration is
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/linux/drivers/clk/mmp/
H A Dclk-gate.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
15 #include "clk.h"
31 if (gate->lock) in mmp_clk_gate_enable()
32 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
34 tmp = readl(gate->reg); in mmp_clk_gate_enable()
35 tmp &= ~gate->mask; in mmp_clk_gate_enable()
36 tmp |= gate->val_enable; in mmp_clk_gate_enable()
37 writel(tmp, gate->reg); in mmp_clk_gate_enable()
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/linux/drivers/iio/adc/
H A Dcc10001_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 Imagination Technologies Ltd.
6 #include <linux/clk.h>
7 #include <linux/delay.h>
47 * As per device specification, wait six clock cycles after power-up to
48 * activate START. Since adding two more clock cycles delay does not
49 * impact the performance too much, we are adding two additional cycles delay
56 struct clk *adc_clk;
69 writel(val, adc_dev->reg_base + reg); in cc10001_adc_write_reg()
75 return readl(adc_dev->reg_base + reg); in cc10001_adc_read_reg()
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H A Dti-ads1298.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2023 - 2024 Topic Embedded Products
8 #include <linux/clk.h>
10 #include <linux/delay.h>
94 /* For reading and writing registers, we need a 3-byte buffer */
96 /* Outputs status word and 'n' 24-bit samples, plus the command byte */
106 struct clk *clk; member
119 * >2 = Multiple DRDY during transfer, lost rdata_xfer_busy - 2 samples
173 .tx_buf = priv->cmd_buffer, in ads1298_write_cmd()
174 .rx_buf = priv->cmd_buffer, in ads1298_write_cmd()
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/linux/drivers/clocksource/
H A Dtimer-fttmr010.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
18 #include <linux/clk.h>
21 #include <linux/delay.h>
81 * - aspeed timer overflow interrupt is controlled by bits in Control
83 * - aspeed timers always generate interrupt when either one of the
112 * A local singleton used by sched_clock and delay timer reads, which are
124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
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H A Dtimer-microchip-pit64b.c1 // SPDX-License-Identifier: GPL-2.0
3 * 64-bit Periodic Interval Timer driver
10 #include <linux/clk.h>
12 #include <linux/delay.h>
51 * struct mchp_pit64b_timer - PIT64B timer data structure
59 struct clk *pclk;
60 struct clk *gclk;
65 * struct mchp_pit64b_clkevt - PIT64B clockevent data structure
79 * struct mchp_pit64b_clksrc - PIT64B clocksource data structure
94 /* Default cycles for clockevent timer. */
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H A Dtimer-sun5i.c1 // SPDX-License-Identifier: GPL-2.0
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/clk.h>
13 #include <linux/delay.h>
38 struct clk *clk; member
53 * When we disable a timer, we need to wait at least for 2 cycles of
60 u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
62 while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
68 u32 val = readl(ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
69 writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
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H A Dtimer-imx-tpm.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/clk.h>
9 #include <linux/delay.h>
13 #include "timer-of.h"
103 * contention between GPU and A7 may results a few cycles delay in tpm_set_next_event()
107 return (now - prev) >= delta ? -ETIME : 0; in tpm_set_next_event()
130 evt->event_handler(evt); in tpm_timer_interrupt()
167 "imx-tpm", in tpm_clocksource_init()
179 GENMASK(counter_width - 1, in tpm_clockevent_init()
185 struct clk *ipg; in tpm_timer_init()
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/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
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/linux/arch/arm/mach-omap1/
H A Dtimer32k.c2 * linux/arch/arm/mach-omap1/timer32k.c
6 * Copyright (C) 2004 - 2005 Nokia Corporation
10 * OMAP Dual-mode timer framework support by Timo Teras
39 #include <linux/delay.h>
44 #include <linux/clk.h>
58 * ---------------------------------------------------------------------------
66 * ---------------------------------------------------------------------------
79 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
82 #define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
129 .name = "32k-timer",
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/linux/drivers/rtc/
H A Drtc-renesas-rtca3.c1 // SPDX-License-Identifier: GPL-2.0
3 * On-Chip RTC Support available on RZ/G3S SoC
10 #include <linux/clk.h>
12 #include <linux/delay.h>
93 * enum rtca3_alrm_set_step - RTCA3 alarm set steps
105 * struct rtca3_ppb_per_cycle - PPB per cycle
115 * struct rtca3_priv - RTCA3 private data structure
140 tmp = readb(priv->base + off); in rtca3_byte_update_bits()
143 writeb(tmp, priv->base + off); in rtca3_byte_update_bits()
150 val = readb(priv->base + RTCA3_RSR); in rtca3_alarm_handler_helper()
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/linux/drivers/nvmem/
H A Dmxs-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale MXS On-Chip OTP driver
9 #include <linux/clk.h>
10 #include <linux/delay.h>
15 #include <linux/nvmem-provider.h>
32 struct clk *clk; member
42 while (timeout--) { in mxs_ocotp_wait()
43 status = readl(otp->base); in mxs_ocotp_wait()
52 return -EBUSY; in mxs_ocotp_wait()
54 return -EIO; in mxs_ocotp_wait()
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8060-dragonboard.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/leds/common.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
7 #include "qcom-msm8660.dtsi"
12 compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";
19 stdout-path = "serial0:115200n8";
23 vph: regulator-fixed {
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/linux/drivers/net/ethernet/ti/
H A Dam65-cpts.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
23 #include "am65-cpts.h"
164 struct clk *refclk;
201 #define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
202 #define am65_cpts_read32(c, r) readl(&(c)->reg->r)
219 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7; in am65_cpts_set_add_val()
221 am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val); in am65_cpts_set_add_val()
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/linux/drivers/regulator/
H A Dti-abb-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2012-2013 Texas Instruments, Inc.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
26 * FAST_OPP: sets ABB LDO to Forward Body-Bias
27 * SLOW_OPP: sets ABB LDO to Reverse Body-Bias
34 * struct ti_abb_info - ABB information per voltage setting
47 * struct ti_abb_reg - Register description for ABB block
50 * @sr2_wtcnt_value_mask: setup register- sr2_wtcnt_value mask
51 * @fbb_sel_mask: setup register- FBB sel mask
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/linux/drivers/mmc/host/
H A Dsdhci-of-dwcmshc.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/arm-smccc.h>
13 #include <linux/clk.h>
14 #include <linux/dma-mapping.h>
24 #include "sdhci-pltfm.h"
41 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
51 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
53 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
151 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */
153 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */
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/linux/drivers/pmdomain/imx/
H A Dgpc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
4 * Copyright 2011-2013 Freescale Semiconductor, Inc.
7 #include <linux/clk.h>
8 #include <linux/delay.h>
47 struct clk *clk[GPC_CLK_MAX]; member
67 regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PDNSCR_OFFS, &val); in imx6_pm_domain_power_off()
72 regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS, in imx6_pm_domain_power_off()
76 val = BIT(pd->cntr_pdn_bit); in imx6_pm_domain_power_off()
77 regmap_update_bits(pd->regmap, GPC_CNTR, val, val); in imx6_pm_domain_power_off()
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