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/linux/arch/powerpc/mm/ptdump/
H A Dbook3s64.c1 // SPDX-License-Identifier: GPL-2.0
14 .mask = _PAGE_PRIVILEGED,
17 .clear = " ",
19 .mask = _PAGE_READ,
22 .clear = " ",
24 .mask = _PAGE_WRITE,
27 .clear = " ",
29 .mask = _PAGE_EXEC,
32 .clear = " ",
34 .mask = _PAGE_PTE,
[all …]
H A Dshared.c1 // SPDX-License-Identifier: GPL-2.0
14 .mask = _PAGE_READ,
17 .clear = "r",
19 .mask = _PAGE_WRITE,
22 .clear = "w",
24 .mask = _PAGE_EXEC,
27 .clear = " ",
29 .mask = _PAGE_PRESENT,
32 .clear = " ",
34 .mask = _PAGE_COHERENT,
[all …]
H A D8xx.c1 // SPDX-License-Identifier: GPL-2.0
15 .mask = _PAGE_HUGE,
18 .mask = _PAGE_SPS,
22 .clear = " ",
24 .mask = _PAGE_RO | _PAGE_NA,
28 .mask = _PAGE_RO | _PAGE_NA,
32 .mask = _PAGE_RO | _PAGE_NA,
36 .mask = _PAGE_EXEC,
39 .clear = " ",
41 .mask = _PAGE_PRESENT,
[all …]
H A Dhashpagetable.c1 // SPDX-License-Identifier: GPL-2.0-only
49 { -1, NULL },
53 u64 mask; member
56 const char *clear; member
63 .mask = SLB_VSID_B,
66 .clear = "ssize: 1T ",
68 .mask = HPTE_V_SECONDARY,
71 .clear = "primary ",
73 .mask = HPTE_V_VALID,
76 .clear = "invalid",
[all …]
/linux/include/linux/amba/
H A Dserial.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/include/asm-arm/hardware/serial_amba.h
20 /* -------------------------------------------------------------------------------
22 * -------------------------------------------------------------------------------
27 #define UART01x_ECR 0x04 /* Error clear register (Write). */
36 #define UART010_ICR 0x1C /* Interrupt clear register (Write). */
45 #define UART011_IMSC 0x38 /* Interrupt mask. */
48 #define UART011_ICR 0x44 /* Interrupt clear register. */
58 #define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */
175 #define UART011_OEIM BIT(10) /* overrun error interrupt mask */
[all …]
/linux/arch/arm64/mm/
H A Dptdump.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <asm/pgtable-hwdef.h>
43 .mask = PTE_VALID,
46 .clear = "F",
48 .mask = PTE_USER,
51 .clear = " ",
53 .mask = PTE_RDONLY,
56 .clear = "RW",
58 .mask = PTE_PXN,
61 .clear = "x ",
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,versatile-fpga-irq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,versatile-fpga-irq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
20 const: arm,versatile-fpga-irq
22 interrupt-controller: true
24 '#interrupt-cells':
30 clear-mask:
31 description: A mask written to clear all IRQs on the controller at boot.
[all …]
/linux/drivers/s390/scsi/
H A Dzfcp_erp.c1 // SPDX-License-Identifier: GPL-2.0
30 * Eyecatcher pseudo flag to bitwise or-combine with enum zfcp_erp_act_type.
36 * Eyecatcher pseudo flag to bitwise or-combine with enum zfcp_erp_act_type.
51 static void zfcp_erp_adapter_block(struct zfcp_adapter *adapter, int mask) in zfcp_erp_adapter_block() argument
54 ZFCP_STATUS_COMMON_UNBLOCKED | mask); in zfcp_erp_adapter_block()
61 list_for_each_entry(curr_act, &act->adapter->erp_running_head, list) in zfcp_erp_action_is_running()
69 struct zfcp_adapter *adapter = act->adapter; in zfcp_erp_action_ready()
71 list_move(&act->list, &adapter->erp_ready_head); in zfcp_erp_action_ready()
73 wake_up(&adapter->erp_ready_wq); in zfcp_erp_action_ready()
79 act->status |= ZFCP_STATUS_ERP_DISMISSED; in zfcp_erp_action_dismiss()
[all …]
/linux/arch/arm/mm/
H A Ddump.c1 // SPDX-License-Identifier: GPL-2.0-only
33 { -1, NULL },
60 u64 mask; member
63 const char *clear; member
70 .mask = L_PTE_USER,
73 .clear = " ",
75 .mask = L_PTE_RDONLY,
78 .clear = "RW",
81 .mask = L_PTE_XN,
84 .clear = "x ",
[all …]
/linux/drivers/media/rc/
H A Dwinbond-cir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
12 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
26 * o Wake-On-CIR functionality
44 #include <media/rc-core.h>
46 #define DRVNAME "winbond-cir"
48 /* CEIR Wake-Up Registers, relative to data->wbase */
60 /* CEIR Enhanced Functionality Registers, relative to data->ebase */
67 /* SP3 Banked Registers, relative to data->sbase */
114 /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
[all …]
/linux/tools/testing/selftests/tc-testing/tc-tests/actions/
H A Dpedit.json23 …"matchPattern": "action order [0-9]+: pedit action pass keys 1.*index 1 ref.*key #0 at ipv4\\+8:…
51 …"matchPattern": "action order [0-9]+: pedit action pass keys 1.*index 90 ref.*key #0 at ipv4\\+8…
79 "matchPattern": "12: val 90abcdef mask 00000000",
135 "matchPattern": "val 12340000 mask 0000ffff.*val 00005678 mask ffff0000",
191 "matchPattern": " 16: add 0f000000 mask 00ffffff",
216 …"matchPattern": "val 12000000 mask 00ffffff.*val 00340000 mask ff00ffff.*val 00005600 mask ffff00f…
224 "name": "Add pedit action with RAW_OP offset u8-u16-u8",
244 …"matchPattern": "val 12000000 mask 00ffffff.*val 00345600 mask ff0000ff.*val 00000078 mask ffffff0…
252 "name": "Add pedit action with RAW_OP offset u16-u8-u8",
272 …"matchPattern": "val 12340000 mask 0000ffff.*val 00005600 mask ffff00ff.*val 00000078 mask ffffff0…
[all …]
/linux/arch/parisc/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
34 ** We don't have DMA channels... well V-class does but the
36 ** Note: this is not relevant right now for PA-RISC, but we cannot
38 ** won't compile :-(
43 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
55 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
57 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
59 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
60 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
[all …]
/linux/lib/
H A Dstmp_device.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
22 * Clear the bit and poll it cleared. This is usually called with
23 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
26 static int stmp_clear_poll_bit(void __iomem *addr, u32 mask) in stmp_clear_poll_bit() argument
30 writel(mask, addr + STMP_OFFSET_REG_CLR); in stmp_clear_poll_bit()
32 while ((readl(addr) & mask) && --timeout) in stmp_clear_poll_bit()
43 /* clear and poll SFTRST */ in stmp_reset_block()
48 /* clear CLKGATE */ in stmp_reset_block()
56 while ((!(readl(reset_addr) & STMP_MODULE_CLKGATE)) && --timeout) in stmp_reset_block()
[all …]
/linux/fs/xfs/scrub/
H A Dhealth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2019-2023 Oracle. All Rights Reserved.
21 * Scrub and In-Core Filesystem Health Assessments
26 * cross-reference records between data structures. Therefore, scrub is in a
40 * 3. If the scrubber finds that A is clean, use sick_mask to clear the incore
51 * 6. If repair rebuilds A correctly and the subsequent re-scrub of A is clean,
52 * use sick_mask to clear the incore sick flags. This should have the effect
55 * 7. If repair rebuilds A incorrectly, the re-scrub will find it corrupt and
67 * of 5-7 still apply, but with a sick_mask that covers everything being
71 /* Map our scrub type to a sick mask and a set of health update functions. */
[all …]
/linux/arch/mips/lib/
H A Dbitops.c6 * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
16 * __mips_set_bit - Atomically set a bit in memory. This is called by
25 unsigned long mask; in __mips_set_bit() local
28 mask = 1UL << bit; in __mips_set_bit()
30 *a |= mask; in __mips_set_bit()
37 * __mips_clear_bit - Clears a bit in memory. This is called by clear_bit() if
39 * @nr: Bit to clear
46 unsigned long mask; in __mips_clear_bit() local
49 mask = 1UL << bit; in __mips_clear_bit()
51 *a &= ~mask; in __mips_clear_bit()
[all …]
/linux/arch/arm/mach-omap2/
H A Dsram242x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram242x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
50 mvn r9, #0x4 @ mask to get clear bit2
51 and r10, r10, r9 @ clear bit2 for lock mode.
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
[all …]
H A Dsram243x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram243x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
50 mvn r9, #0x4 @ mask to get clear bit2
51 and r10, r10, r9 @ clear bit2 for lock mode.
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
[all …]
/linux/drivers/net/phy/
H A Dphy-core.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include "phylib-internal.h"
11 #include "phy-caps.h"
14 * phy_speed_to_str - Return a string representing the PHY link speed
61 return "Unsupported (update phy-core.c)"; in phy_speed_to_str()
67 * phy_duplex_to_str - Return string describing the duplex
79 return "Unsupported (update phy-core.c)"; in phy_duplex_to_str()
84 * phy_rate_matching_to_str - Return a string describing the rate matching
98 return "open-loop"; in phy_rate_matching_to_str()
100 return "Unsupported (update phy-core.c)"; in phy_rate_matching_to_str()
[all …]
/linux/drivers/media/platform/imagination/
H A De5010-jpeg-enc-hw.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
7 * Author: David Huang <d-huang@ti.com>
14 #include "e5010-jpeg-enc-hw.h"
16 static void write_reg_field(void __iomem *base, unsigned int offset, u32 mask, in write_reg_field() argument
22 if (mask != 0xffffffff) { in write_reg_field()
24 value = (value & mask) | (reg & ~mask); in write_reg_field()
30 unsigned int offset, u32 mask, unsigned int shift, in write_reg_field_not_busy() argument
42 write_reg_field(wr_base, offset, mask, shift, value); in write_reg_field_not_busy()
241 void e5010_hw_clear_output_error(void __iomem *core_base, u32 clear) in e5010_hw_clear_output_error() argument
[all …]
/linux/fs/hfs/
H A Dbitmap.c4 * Copyright (C) 1996-1997 Paul H. Hargrove
11 * search/set/clear bits.
21 * determine the number of the first zero bits (in left-to-right ordering)
26 * Accesses memory in 32-bit aligned chunks of 32-bits and thus
32 u32 mask, start, len, n; in hfs_find_set_zero_bits() local
48 mask = (1U << 31) >> i; in hfs_find_set_zero_bits()
49 for (; i < 32; mask >>= 1, i++) { in hfs_find_set_zero_bits()
50 if (!(n & mask)) in hfs_find_set_zero_bits()
60 mask = 1 << 31; in hfs_find_set_zero_bits()
61 for (i = 0; i < 32; mask >>= 1, i++) { in hfs_find_set_zero_bits()
[all …]
/linux/arch/sh/boards/mach-se/7724/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0
21 #include <mach-se/mach/se7724.h>
26 unsigned short mask; member
50 set.mask = IRQ0_MASK; in get_fpga_irq()
56 set.mask = IRQ1_MASK; in get_fpga_irq()
62 set.mask = IRQ2_MASK; in get_fpga_irq()
72 unsigned int irq = data->irq; in disable_se7724_irq()
74 unsigned int bit = irq - set.base; in disable_se7724_irq()
80 unsigned int irq = data->irq; in enable_se7724_irq()
82 unsigned int bit = irq - set.base; in enable_se7724_irq()
[all …]
/linux/arch/x86/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * controller 1: channels 0-3, byte operations, ports 00-1F
27 * controller 2: channels 4-7, word operations, ports C0-DF
29 * - ALL registers are 8 bits only, regardless of transfer size
30 * - channel 4 is not used - cascades 1 into 2.
31 * - channels 0-3 are byte - addresses/counts are for physical bytes
32 * - channels 5-7 are word - addresses/counts are for physical words
33 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
34 * - transfer count loaded to registers is 1 less than actual count
35 * - controller 2 offsets are all even (2x offsets for controller 1)
[all …]
/linux/arch/mips/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 * controller 1: channels 0-3, byte operations, ports 00-1F
33 * controller 2: channels 4-7, word operations, ports C0-DF
35 * - ALL registers are 8 bits only, regardless of transfer size
36 * - channel 4 is not used - cascades 1 into 2.
37 * - channels 0-3 are byte - addresses/counts are for physical bytes
38 * - channels 5-7 are word - addresses/counts are for physical words
39 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
40 * - transfer count loaded to registers is 1 less than actual count
41 * - controller 2 offsets are all even (2x offsets for controller 1)
[all …]
/linux/drivers/soc/mediatek/
H A Dmtk-infracfg.c1 // SPDX-License-Identifier: GPL-2.0-only
17 * mtk_infracfg_set_bus_protection - enable bus protection
19 * @mask: The mask containing the protection bits to be enabled.
28 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
35 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
36 mask); in mtk_infracfg_set_bus_protection()
38 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
41 val, (val & mask) == mask, in mtk_infracfg_set_bus_protection()
48 * mtk_infracfg_clear_bus_protection - disable bus protection
50 * @mask: The mask containing the protection bits to be disabled.
[all …]
/linux/arch/arm/mach-pxa/
H A Dpxa3xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/pxa3xx.c
9 * 2007-09-02: eric miao <eric.miao@marvell.com>
13 #include <linux/dma/pxa-dma.h>
17 #include <linux/gpio-pxa.h>
25 #include <linux/platform_data/i2c-pxa.h>
32 #include "pxa3xx-regs.h"
34 #include <linux/platform_data/usb-ohci-pxa27x.h>
36 #include "addr-map.h"
72 * We disable FIQs across the standby - otherwise, we might receive a
[all …]

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