1 // SPDX-License-Identifier: GPL-2.0-only
3  * linux/arch/arm/mach-pxa/pxa3xx.c
9  * 2007-09-02: eric miao <eric.miao@marvell.com>
13 #include <linux/dma/pxa-dma.h>
17 #include <linux/gpio-pxa.h>
25 #include <linux/platform_data/i2c-pxa.h>
32 #include "pxa3xx-regs.h"
34 #include <linux/platform_data/usb-ohci-pxa27x.h>
36 #include "addr-map.h"
72  * We disable FIQs across the standby - otherwise, we might receive a
80 		    pm_enter_standby_end - pm_enter_standby_start);  in pxa3xx_cpu_standby()
123 	/* clear and setup wakeup source */  in pxa3xx_cpu_pm_suspend()
202 	 * Clear the resume enable registers.  in pxa3xx_init_pm()
214 	unsigned long flags, mask = 0;  in pxa3xx_set_wake()  local
216 	switch (d->irq) {  in pxa3xx_set_wake()
218 		mask = ADXER_MFP_WSSP3;  in pxa3xx_set_wake()
221 		mask = ADXER_WMSL0;  in pxa3xx_set_wake()
225 		mask = ADXER_WUSBH;  in pxa3xx_set_wake()
228 		mask = ADXER_WKP;  in pxa3xx_set_wake()
231 		mask = ADXER_MFP_WAC97;  in pxa3xx_set_wake()
234 		mask = ADXER_WUSIM0;  in pxa3xx_set_wake()
237 		mask = ADXER_MFP_WSSP2;  in pxa3xx_set_wake()
240 		mask = ADXER_MFP_WI2C;  in pxa3xx_set_wake()
243 		mask = ADXER_MFP_WUART3;  in pxa3xx_set_wake()
246 		mask = ADXER_MFP_WUART2;  in pxa3xx_set_wake()
249 		mask = ADXER_MFP_WUART1;  in pxa3xx_set_wake()
252 		mask = ADXER_MFP_WMMC1;  in pxa3xx_set_wake()
255 		mask = ADXER_MFP_WSSP1;  in pxa3xx_set_wake()
258 		mask = ADXER_WRTC;  in pxa3xx_set_wake()
261 		mask = ADXER_MFP_WSSP4;  in pxa3xx_set_wake()
264 		mask = ADXER_WTSI;  in pxa3xx_set_wake()
267 		mask = ADXER_WUSIM1;  in pxa3xx_set_wake()
270 		mask = ADXER_MFP_WMMC2;  in pxa3xx_set_wake()
273 		mask = ADXER_MFP_WFLASH;  in pxa3xx_set_wake()
276 		mask = ADXER_WUSB2;  in pxa3xx_set_wake()
279 		mask = ADXER_WEXTWAKE0;  in pxa3xx_set_wake()
282 		mask = ADXER_WEXTWAKE1;  in pxa3xx_set_wake()
285 		mask = ADXER_MFP_GEN12;  in pxa3xx_set_wake()
288 		return -EINVAL;  in pxa3xx_set_wake()
293 		wakeup_src |= mask;  in pxa3xx_set_wake()
295 		wakeup_src &= ~mask;  in pxa3xx_set_wake()
307 	PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);  in pxa_ack_ext_wakeup()
313 	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);  in pxa_mask_ext_wakeup()
319 	PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);  in pxa_unmask_ext_wakeup()
325 		PWER |= 1 << (d->irq - IRQ_WAKEUP0);  in pxa_set_ext_wakeup_type()
328 		PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);  in pxa_set_ext_wakeup_type()
375 IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq);
407 		 * clear RDH bit every time after reset  in pxa3xx_init()
409 		 * Note: the last 3 bits DxS are write-1-to-clear so carefully  in pxa3xx_init()