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/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Docelot-reset.txt1 Microsemi Ocelot reset controller
3 The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
6 The reset registers are both present in the MSCC vcoreiii MIPS and
11 - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
12 "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
15 reset@1070008 {
16 compatible = "mscc,ocelot-chip-reset";
/freebsd/sys/contrib/device-tree/Bindings/net/nfc/
H A Dnfcmrvl.txt4 - compatible: Should be:
5 - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices
6 - "marvell,nfc-i2c" for I2C devices
7 - "marvell,nfc-spi" for SPI devices
10 - pinctrl-names: Contains only one value - "default".
11 - pintctrl-0: Specifies the pin control groups used for this controller.
12 - reset-n-io: Output GPIO pin used to reset the chip (active low).
13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames.
15 Optional UART-based chip specific properties:
16 - flow-control: Specifies that the chip is using RTS/CTS.
[all …]
H A Dmarvell,nci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Djedec,spi-nor.txt4 - #address-cells, #size-cells : Must be present if the device has sub-nodes
6 - compatible : May include a device-specific string consisting of the
7 manufacturer and name of the chip. A list of supported chip
9 Must also include "jedec,spi-nor" for any SPI NOR flash that can
12 Supported chip names:
50 The following chip names have been used historically to
53 m25p05-nonjedec
54 m25p10-nonjedec
55 m25p20-nonjedec
56 m25p40-nonjedec
[all …]
H A Dcadence-quadspi.txt4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dmarvell,berlin2-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/reset/marvell,berlin2-reset.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell Berlin reset controller
11 - Antoine Tenart <atenart@kernel.org>
13 description: The reset controller node must be a sub-node of the chip
18 const: marvell,berlin2-reset
20 "#reset-cells":
24 - compatible
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dcyttsp.txt4 - compatible : must be "cypress,cyttsp-i2c" or "cypress,cyttsp-spi"
5 - reg : Device I2C address or SPI chip select number
6 - spi-max-frequency : Maximum SPI clocking speed of the device (for cyttsp-spi)
7 - interrupts : (gpio) interrupt to which the chip is connected
9 - bootloader-key : the 8-byte bootloader key that is required to switch
10 the chip from bootloader mode (default mode) to
16 - reset-gpios : the reset gpio the chip is connected to
18 - touchscreen-size-x : horizontal resolution of touchscreen (in pixels)
19 - touchscreen-size-y : vertical resolution of touchscreen (in pixels)
20 - touchscreen-fuzz-x : horizontal noise value of the absolute input device
[all …]
H A Dzforce_ts.txt4 - compatible: must be "neonode,zforce"
5 - reg: I2C address of the chip
6 - interrupts: interrupt to which the chip is connected
7 - reset-gpios: reset gpio the chip is connected to
8 - x-size: horizontal resolution of touchscreen
9 - y-size: vertical resolution of touchscreen
12 - irq-gpios : interrupt gpio the chip is connected to
13 - vdd-supply: Regulator controlling the controller supply
24 vdd-supply = <&reg_zforce_vdd>;
26 reset-gpios = <&gpio5 9 0>; /* RST */
[all …]
H A Dpixcir_i2c_ts.txt4 - compatible: must be "pixcir,pixcir_ts" or "pixcir,pixcir_tangoc"
5 - reg: I2C address of the chip
6 - interrupts: interrupt to which the chip is connected
7 - attb-gpio: GPIO connected to the ATTB line of the chip
8 - touchscreen-size-x: horizontal resolution of touchscreen (in pixels)
9 - touchscreen-size-y: vertical resolution of touchscreen (in pixels)
12 - reset-gpios: GPIO connected to the RESET line of the chip
13 - enable-gpios: GPIO connected to the ENABLE line of the chip
14 - wake-gpios: GPIO connected to the WAKE line of the chip
25 attb-gpio = <&gpf 2 0 2>;
[all …]
H A Dbu21029.txt4 - compatible : must be "rohm,bu21029"
5 - reg : i2c device address of the chip (0x40 or 0x41)
6 - interrupt-parent : the phandle for the gpio controller
7 - interrupts : (gpio) interrupt to which the chip is connected
8 - rohm,x-plate-ohms : x-plate resistance in Ohm
11 - reset-gpios : gpio pin to reset the chip (active low)
12 - touchscreen-size-x : horizontal resolution of touchscreen (in pixels)
13 - touchscreen-size-y : vertical resolution of touchscreen (in pixels)
14 - touchscreen-max-pressure: maximum pressure value
15 - vdd-supply : power supply for the controller
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dnvidia,tegra20-gmi.txt10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
20 - #size-cells: The number of cells used to represent the size of an address
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dsilabs,wfx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jérôme Pouiller <jerome.pouiller@silabs.com>
14 Support for the Wifi chip WFxxx from Silicon Labs. Currently, the only device
16 https://www.silabs.com/documents/public/data-sheets/wf200-datasheet.pdf
22 Declaring the WFxxx chip in device tree is mandatory (usually, the VID/PID is
25 It is recommended to declare a mmc-pwrseq on SDIO host above WFx. Without
26 it, you may encounter issues during reboot. The mmc-pwrseq should be
27 compatible with mmc-pwrseq-simple. Please consult
[all …]
/freebsd/sys/contrib/device-tree/Bindings/staging/net/wireless/
H A Dsilabs,wfx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jérôme Pouiller <jerome.pouiller@silabs.com>
15 Support for the Wifi chip WFxxx from Silicon Labs. Currently, the only device
17 https://www.silabs.com/documents/public/data-sheets/wf200-datasheet.pdf
23 Declaring the WFxxx chip in device tree is mandatory (usually, the VID/PID is
26 It is recommended to declare a mmc-pwrseq on SDIO host above WFx. Without
27 it, you may encounter issues during reboot. The mmc-pwrseq should be
28 compatible with mmc-pwrseq-simple. Please consult
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dov5645.txt1 * Omnivision 1/4-Inch 5Mp CMOS Digital Image Sensor
3 The Omnivision OV5645 is a 1/4-Inch CMOS active pixel digital image sensor with
8 - compatible: Value should be "ovti,ov5645".
9 - clocks: Reference to the xclk clock.
10 - clock-names: Should be "xclk".
11 - clock-frequency: Frequency of the xclk clock.
12 - enable-gpios: Chip enable GPIO. Polarity is GPIO_ACTIVE_HIGH. This corresponds
14 - reset-gpios: Chip reset GPIO. Polarity is GPIO_ACTIVE_LOW. This corresponds to
16 - vdddo-supply: Chip digital IO regulator.
17 - vdda-supply: Chip analog regulator.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Daltera-a10sr.txt1 * Altera Arria10 Development Kit System Resource Chip
4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
7 System Resource chip
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dnvidia,tegra20-usb-phy.txt6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
10 - reg : Defines the following set of registers, in the order listed:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
16 - clocks : Defines the clocks listed in the clock-names property.
17 - clock-names : The following clock names must be present:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dst,stih4xx.txt3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/powerpc/4xx/
H A Dreboot.txt4 software reset mechanism may be overridden. Here the possible values of
7 1 - PPC4xx core reset
8 2 - PPC4xx chip reset
9 3 - PPC4xx system reset (default)
17 reset-type = <2>; /* Use chip-reset */
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dsyna.txt3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
18 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
20 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
26 model = "Sony NSZ-GS7";
27 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
38 - compatible: should be "marvell,berlin-cpu-ctrl"
39 - reg: address and length of the register set
43 cpu-ctrl@f7dd0000 {
44 compatible = "marvell,berlin-cpu-ctrl";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-mcp23s08.txt2 8-/16-bit I/O expander with serial interface (I2C/SPI)
5 - compatible : Should be
6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version
7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or
9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
11 - "microchip,mcp23s08" for 8 GPIO SPI version
12 - "microchip,mcp23s17" for 16 GPIO SPI version
13 - "microchip,mcp23s18" for 16 GPIO SPI version
14 - "microchip,mcp23008" for 8 GPIO I2C version or
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dstericsson,u8500-clks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
[all …]
/freebsd/sys/dev/wbwd/
H A Dwbwd.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
79 #define WB_LDN8_CRF5_KBRST 0x02 /* 1: timeout causes pin60 kbd reset */
88 #define WB_LDN8_CRF7_FORCE 0x20 /* 1: force timeout (self-clear) */
100 enum chips chip; member
109 * re-load it periodically.
117 * register as these might be different by chip.
126 enum chips chip; member
131 .chip = w83627hf,
136 .chip = w83627s,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dcadence-quadspi.txt4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
9 - reg : Contains two entries, each of which is a tuple consisting of a
13 - interrupts : Unit interrupt specifier for the controller interrupt.
14 - clocks : phandle to the Quad SPI clock.
15 - cdns,fifo-depth : Size of the data FIFO in words.
16 - cdns,fifo-width : Bus width of the data FIFO in bytes.
[all …]

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