1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
79 #define	WB_LDN8_CRF5_KBRST	0x02	/* 1: timeout causes pin60 kbd reset */
88 #define	WB_LDN8_CRF7_FORCE	0x20	/* 1: force timeout (self-clear) */
100 	enum chips		chip;  member
109 	 * re-load it periodically.
117 	 * register as these might be different by chip.
126 	enum chips		chip;  member
131 		.chip		= w83627hf,
136 		.chip		= w83627s,
141 		.chip		= w83697hf,
146 		.chip		= w83697ug,
151 		.chip		= w83637hf,
156 		.chip		= w83627thf,
161 		.chip		= w83687thf,
166 		.chip		= w83627ehf,
171 		.chip		= w83627dhg,
176 		.chip		= w83627uhg,
181 		.chip		= w83667hg,
186 		.chip		= w83627dhg_p,
187 		.descr		= "Winbond 83627DHG-P",
191 		.chip		= w83667hg_b,
192 		.descr		= "Winbond 83667HG-B",
196 		.chip		= nct6775,
201 		.chip		= nct6776,
206 		.chip		= nct6102,
211 		.chip		= nct6779,
216 		.chip		= nct6791,
221 		.chip		= nct6792,
226 		.chip		= nct6793,
231 		.chip		= nct6795,
253 	sbuf_printf(&sb, "CR%02X 0x%02x ", sc->ctl_reg, sc->reg_1);  in sysctl_wb_debug()
254 	sbuf_printf(&sb, "CR%02X 0x%02x ", sc->time_reg, sc->reg_timeout);  in sysctl_wb_debug()
255 	sbuf_printf(&sb, "CR%02X 0x%02x", sc->csr_reg, sc->reg_2);  in sysctl_wb_debug()
274 	sc->reg_1 = superio_read(sc->dev, sc->ctl_reg);  in sysctl_wb_debug_current()
275 	sc->reg_timeout = superio_read(sc->dev, sc->time_reg);  in sysctl_wb_debug_current()
276 	sc->reg_2 = superio_read(sc->dev, sc->csr_reg);  in sysctl_wb_debug_current()
289  * XXX-BZ notyet: currently no general infrastructure exists to do this.
300 	val = sc->test_nmi;  in sysctl_wb_force_test_nmi()
305         if (error || !req->newptr)  in sysctl_wb_force_test_nmi()
313 		sc->test_nmi = 0;  in sysctl_wb_force_test_nmi()
322 		sc->test_nmi = 1;  in sysctl_wb_force_test_nmi()
326 	sc->reg_2 = superio_read(sc->dev, sc->csr_reg);  in sysctl_wb_force_test_nmi()
327 	sc->reg_2 |= WB_LDN8_CRF7_FORCE;  in sysctl_wb_force_test_nmi()
328 	superio_write(sc->dev, sc->csr_reg, sc->reg_2);  in sysctl_wb_force_test_nmi()
343 	device_printf(sc->dev, "%s%sWatchdog %sabled. %s"  in wb_print_state()
347 	    (sc->reg_timeout > 0x00) ? "en" : "dis",  in wb_print_state()
348 	    (sc->reg_2 & WB_LDN8_CRF7_TS) ? "Watchdog fired. " : "",  in wb_print_state()
349 	    (sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1,  in wb_print_state()
350 	    sc->reg_timeout,  in wb_print_state()
351 	    (sc->reg_timeout > 0x00) ? "<" : "",  in wb_print_state()
352 	    sc->reg_timeout * ((sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1),  in wb_print_state()
353 	    (sc->reg_timeout > 0x00) ? " left" : "",  in wb_print_state()
354 	    sc->ctl_reg, sc->reg_1, sc->csr_reg, sc->reg_2);  in wb_print_state()
370 		if (sc->timeout_override > 0)  in wb_set_watchdog()
371 			timeout = sc->timeout_override;  in wb_set_watchdog()
378 	if (sc->debug_verbose)  in wb_set_watchdog()
383 		sc->reg_timeout = 0;  in wb_set_watchdog()
384 		superio_write(sc->dev, sc->time_reg, sc->reg_timeout);  in wb_set_watchdog()
388 		sc->reg_1 = superio_read(sc->dev, sc->ctl_reg);  in wb_set_watchdog()
392 			sc->reg_1 |= WB_LDN8_CRF5_SCALE;  in wb_set_watchdog()
393 			sc->reg_timeout = (timeout / 60);  in wb_set_watchdog()
395 				sc->reg_timeout++;  in wb_set_watchdog()
398 			sc->reg_1 &= ~WB_LDN8_CRF5_SCALE;  in wb_set_watchdog()
399 			sc->reg_timeout = timeout;  in wb_set_watchdog()
403 		sc->reg_2 = superio_read(sc->dev, sc->csr_reg);  in wb_set_watchdog()
404 		if (sc->reg_2 & WB_LDN8_CRF7_TS) {  in wb_set_watchdog()
405 			sc->reg_2 &= ~WB_LDN8_CRF7_TS;  in wb_set_watchdog()
406 			superio_write(sc->dev, sc->csr_reg, sc->reg_2);  in wb_set_watchdog()
410 		superio_write(sc->dev, sc->ctl_reg, sc->reg_1);  in wb_set_watchdog()
412 		/* Set timer and arm/reset the watchdog. */  in wb_set_watchdog()
413 		superio_write(sc->dev, sc->time_reg, sc->reg_timeout);  in wb_set_watchdog()
416 	if (sc->debug_verbose)  in wb_set_watchdog()
438 		/* Reset (and arm) watchdog. */  in wb_watchdog_fn()
479 			sc->chip = wb_devs[j].chip;  in wb_probe()
488 		    "unrecognized chip: devid 0x%02x, revid 0x%02x\n",  in wb_probe()
504 	sc->dev = dev;  in wb_attach()
509 	switch (sc->chip) {  in wb_attach()
512 		sc->ctl_reg = 0xf3;  in wb_attach()
513 		sc->time_reg = 0xf4;  in wb_attach()
514 		sc->csr_reg = 0xf7;  in wb_attach()
517 		sc->ctl_reg = 0xf0;  in wb_attach()
518 		sc->time_reg = 0xf1;  in wb_attach()
519 		sc->csr_reg = 0xf2;  in wb_attach()
522 		sc->ctl_reg = 0xf5;  in wb_attach()
523 		sc->time_reg = 0xf6;  in wb_attach()
524 		sc->csr_reg = 0xf7;  in wb_attach()
528 	switch (sc->chip) {  in wb_attach()
551 		t = superio_read(dev, 0x2D) & ~0x01; /* PIN77 -> WDT0# */  in wb_attach()
553 		t = superio_read(dev, sc->ctl_reg);  in wb_attach()
556 		superio_write(dev, sc->ctl_reg, t);  in wb_attach()
561 		t = superio_read(dev, 0x2C) & ~0x80; /* PIN47 -> WDT0# */  in wb_attach()
582 		t = superio_read(dev, sc->ctl_reg);  in wb_attach()
585 		superio_write(dev, sc->ctl_reg, t);  in wb_attach()
592 	sc->reg_1 = superio_read(dev, sc->ctl_reg);  in wb_attach()
593 	sc->reg_timeout = superio_read(dev, sc->time_reg);  in wb_attach()
594 	sc->reg_2 = superio_read(dev, sc->csr_reg);  in wb_attach()
597 	if (bootverbose || (sc->reg_timeout > 0x00))  in wb_attach()
600 	sc->reg_1 &= ~WB_LDN8_CRF5_KEYB_P20;  in wb_attach()
601 	sc->reg_1 |= WB_LDN8_CRF5_KBRST;  in wb_attach()
602 	superio_write(dev, sc->ctl_reg, sc->reg_1);  in wb_attach()
606 	 * Disable timer reset on mouse interrupts.  Leave reset on keyboard,  in wb_attach()
609 	sc->reg_2 &= ~(WB_LDN8_CRF7_MOUSE|WB_LDN8_CRF7_TS);  in wb_attach()
610 	superio_write(dev, sc->csr_reg, sc->reg_2);  in wb_attach()
615 			sc->timeout_override = timeout;  in wb_attach()
620 	    "timeout_override", CTLFLAG_RW, &sc->timeout_override, 0,  in wb_attach()
623 	    "debug_verbose", CTLFLAG_RW, &sc->debug_verbose, 0,  in wb_attach()
638 	sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, wb_watchdog_fn, sc,  in wb_attach()
655 	if (sc->ev_tag)  in wb_detach()
656 		EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);  in wb_detach()