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/linux/drivers/clk/bcm/
H A Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
49 .channel = BCM_SR_GENPLL0_125M_CLK,
52 .mdiv = REG_VAL(0x18, 0, 9),
55 .channel = BCM_SR_GENPLL0_SCR_CLK,
58 .mdiv = REG_VAL(0x18, 10, 9),
61 .channel = BCM_SR_GENPLL0_250M_CLK,
64 .mdiv = REG_VAL(0x18, 20, 9),
[all …]
H A Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
63 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
69 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
75 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
81 .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
83 .enable = ENABLE_VAL(0x4, 9, 3, 15),
[all …]
H A Dclk-ns2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
35 .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
49 .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
55 .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
61 .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
67 .channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
73 .channel = BCM_NS2_GENPLL_SCR_CH4_UNUSED,
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-admaif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
13 Tx channel and ADMA channel receiving data from AHUB pairs with
14 ADMAIF Rx channel.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
[all …]
H A Dsnps,designware-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jose Abreu <joabreu@synopsys.com>
15 - items:
16 - const: canaan,k210-i2s
17 - const: snps,designware-i2s
18 - enum:
19 - snps,designware-i2s
[all …]
H A Dfsl,qmc-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,qmc-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
16 if only one QMC channel is used by the DAI or it is working in non-interleaved
20 - $ref: dai-common.yaml#
24 const: fsl,qmc-audio
26 '#address-cells':
28 '#size-cells':
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr-channel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR channel with chip/rank topology description
10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-natte.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-natte.dts - Device Tree include file for the Natte board
11 mux: mux-controller {
12 compatible = "gpio-mux";
13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
20 batntc-mux {
21 compatible = "io-channel-mux";
22 io-channels = <&adc 5>;
23 io-channel-names = "parent";
[all …]
/linux/Documentation/devicetree/bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
[all …]
/linux/sound/soc/sprd/
H A Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
57 /* Channel water mark definition */
62 /* DMA channel select definition */
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
80 #define MCDT_CH_FIFO_ADDR_MASK GENMASK(9, 0)
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
128 static void sprd_mcdt_dac_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel, in sprd_mcdt_dac_set_watermark() argument
[all …]
/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
72 #define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) argument
82 # define SSI_NOTEMPTY(channel) (1 << (channel)) argument
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dqcom,spmi-vadc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
[all …]
H A Dadi,ad4695.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <Michael.Hennerich@analog.com>
11 - Nuno Sá <nuno.sa@analog.com>
14 A family of similar multi-channel analog to digital converters with SPI bus.
21 $ref: /schemas/spi/spi-peripheral-props.yaml#
26 - adi,ad4695
27 - adi,ad4696
28 - adi,ad4697
[all …]
/linux/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_uw2453.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
20 /* The 3-wire serial interface provides access to 8 write-only registers.
24 /* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
50 RF_CHANNEL( 9) = 0x57,
[all …]
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
65 #define PMT_CTL_RES_CLR_WKP_MASK_ GENMASK(9, 8)
132 #define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8)
152 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
153 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
154 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
157 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
158 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
159 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
234 #define MAC_WUCSR_RFE_WAKE_FR_ BIT(9)
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
31 9: Synchronous Serial Port SSP1
32 10: Multi-Channel Display Engine MCDE RX
[all …]
H A Dcirrus,ep9301-dma-m2p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2p
20 - items:
21 - enum:
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 IEEE 802.11a/g LP-PHY driver
7 Copyright (c) 2008-2009 Michael Buesch <m@bues.ch>
23 static inline u16 channel2freq_lp(u8 channel) in channel2freq_lp() argument
25 if (channel < 14) in channel2freq_lp()
26 return (2407 + 5 * channel); in channel2freq_lp()
27 else if (channel == 14) in channel2freq_lp()
29 else if (channel < 184) in channel2freq_lp()
30 return (5000 + 5 * channel); in channel2freq_lp()
32 return (4000 + 5 * channel); in channel2freq_lp()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dbrcm,asp-v2.0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/brcm,asp-v2.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Justin Chen <justin.chen@broadcom.com>
11 - Florian Fainelli <florian.fainelli@broadcom.com>
18 - items:
19 - enum:
20 - brcm,bcm74165b0-asp
21 - const: brcm,asp-v2.2
[all …]
/linux/drivers/edac/
H A Dx38_edac.c18 #include <linux/io-64-nonatomic-lo-hi.h>
29 /* Intel X38 register addresses - device 0 function 0 - DRAM Controller */
39 * 9:0 total populated physical memory
41 #define X38_TOM_MASK 0x3ff /* bits 9:0 */
55 * 9 LOCK to non-DRAM Memory Flag (LCKF)
59 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
60 * 0 Single-bit DRAM ECC Error Flag (DSERR)
67 /* Intel MMIO register space - device 0 function 0 - MMR space */
69 #define X38_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4)
72 * 9:0 Channel 0 DRAM Rank Boundary Address
[all …]
H A Di3200_edac.c3 * Copyright (C) 2008-2009 Akamai Technologies, Inc.
18 #include <linux/io-64-nonatomic-lo-hi.h>
29 /* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */
39 * 9:0 total populated physical memory
41 #define I3200_TOM_MASK 0x3ff /* bits 9:0 */
55 * 9 LOCK to non-DRAM Memory Flag (LCKF)
59 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
60 * 0 Single-bit DRAM ECC Error Flag (DSERR)
67 /* Intel MMIO register space - device 0 function 0 - MMR space */
69 #define I3200_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4)
[all …]
/linux/Documentation/devicetree/bindings/leds/
H A Dleds-lp55xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp55xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
14 Bindings for the TI/National Semiconductor LP55xx and LP8501 multi channel
27 - national,lp5521
28 - national,lp5523
29 - ti,lp55231
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8822be_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8822bu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8822bs_efuse_parsing()
43 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_read_efuse()
49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7)); in rtw8822b_read_efuse()
50 efuse->rfe_option = map->rfe_option; in rtw8822b_read_efuse()
51 efuse->rf_board_option = map->rf_board_option; in rtw8822b_read_efuse()
52 efuse->crystal_cap = map->xtal_k; in rtw8822b_read_efuse()
[all …]
/linux/sound/pci/ca0106/
H A Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
12 * Removed noise from Center/LFE channel when in Analog mode.
20 * 0.0.9
50 * Implement support for Line-in capture on SB Live 24bit.
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
88 #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
93 #define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
[all …]
/linux/drivers/iio/adc/
H A Dti-ads8344.c1 // SPDX-License-Identifier: GPL-2.0+
3 * ADS8344 16-bit 8-Channel ADC driver
19 #define ADS8344_CHANNEL(channel) ((channel) << 4) argument
26 * Lock protecting access to adc->tx_buff and rx_buff,
39 .channel = chan, \
49 .channel = (chan1), \
67 ADS8344_VOLTAGE_CHANNEL_DIFF(2, 3, 9),
76 static int ads8344_adc_conversion(struct ads8344 *adc, int channel, in ads8344_adc_conversion() argument
79 struct spi_device *spi = adc->spi; in ads8344_adc_conversion()
82 adc->tx_buf = ADS8344_START; in ads8344_adc_conversion()
[all …]

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