| /freebsd/share/man/man4/ |
| H A D | cfi.4 | 1 .\"-
2 .\" Copyright (c) 2015-2016 SRI International
6 .\" Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
34 .Nm cfi ,
36 .Nd driver for Common Flash Interface (CFI) NOR flash
38 .Cd "device cfi"
45 .Cd hint.cfi.0.at="nexus0"
46 .Cd hint.cfi.0.maddr=0x74000000
47 .Cd hint.cfi.0.msize=0x4000000
50 .Cd flash@74000000 {
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | mtd-physmap.txt | 1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
3 Flash chips (Memory Technology Devices) are often used for solid state
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
[all …]
|
| H A D | mtd-physmap.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
13 Flash chips (Memory Technology Devices) are often used for solid state
17 - $ref: mtd.yaml#
18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
23 - items:
[all …]
|
| H A D | intel,ixp4xx-flash.txt | 1 Flash device on Intel IXP4xx SoC
3 This flash is regular CFI compatible (Intel or AMD extended) flash chips with
4 specific big-endian or mixed-endian memory access pattern.
7 - compatible : must be "intel,ixp4xx-flash", "cfi-flash";
8 - reg : memory address for the flash chip
9 - bank-width : width in bytes of flash interface, should be <2>
11 For the rest of the properties, see mtd-physmap.txt.
13 The device tree may optionally contain sub-nodes describing partitions of the
18 flash@50000000 {
19 compatible = "intel,ixp4xx-flash", "cfi-flash";
[all …]
|
| H A D | cortina,gemini-flash.txt | 1 Flash device on Cortina Systems Gemini SoC
3 This flash is regular CFI compatible (Intel or AMD extended) flash chips with
7 - compatible : must be "cortina,gemini-flash", "cfi-flash";
8 - reg : memory address for the flash chip
9 - syscon : must be a phandle to the system controller
10 - bank-width : width in bytes of flash interface, should be <2>
12 For the rest of the properties, see mtd-physmap.yaml.
14 The device tree may optionally contain sub-nodes describing partitions of the
19 flash@30000000 {
20 compatible = "cortina,gemini-flash", "cfi-flash";
[all …]
|
| H A D | arm-versatile.txt | 1 Flash device on ARM Versatile board
3 These flash chips are found in the ARM reference designs like Integrator,
6 They are regular CFI compatible (Intel or AMD extended) flash chips with
11 - compatible : must be "arm,versatile-flash", "cfi-flash";
12 - reg : memory address for the flash chip
13 - bank-width : width in bytes of flash interface.
15 For the rest of the properties, see mtd-physmap.txt.
17 The device tree may optionally contain sub-nodes describing partitions of the
22 flash@34000000 {
23 compatible = "arm,versatile-flash", "cfi-flash";
[all …]
|
| H A D | cypress,hyperflash.txt | 1 Bindings for HyperFlash NOR flash chips compliant with Cypress HyperBus
2 specification and supports Cypress CFI specification 1.5 command set.
5 - compatible : "cypress,hyperflash", "cfi-flash" for HyperFlash NOR chips
6 - reg : Address of flash's memory map
10 flash@0 {
11 compatible = "cypress,hyperflash", "cfi-flash";
|
| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | pl353-smc.txt | 8 - compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell".
9 - reg : Controller registers map and length.
10 - clock-names : List of input clock names - "memclk", "apb_pclk"
12 - clocks : Clock phandles (see clock bindings for details).
13 - address-cells : Must be 2.
14 - size-cells : Must be 1.
17 For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
24 smcc: memory-controller@e000e000
25 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
26 clock-names = "memclk", "apb_pclk";
[all …]
|
| H A D | renesas,rpc-if.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Reduced Pin Count Interface (RPC-IF)
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
13 Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
16 The flash chip itself should be represented by a subnode of the RPC-IF node.
17 The flash interface is selected based on the "compatible" property of this
19 - if it contains "jedec,spi-nor", then SPI is used;
[all …]
|
| H A D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
|
| /freebsd/sys/dev/bhnd/cores/chipc/ |
| H A D | chipc.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
42 * Supported ChipCommon flash types.
45 CHIPC_FLASH_NONE = 0, /**< No flash, or a type unrecognized
47 CHIPC_PFLASH_CFI = 1, /**< CFI-compatible parallel flash */
48 CHIPC_SFLASH_ST = 2, /**< ST serial flash */
49 CHIPC_SFLASH_AT = 3, /**< Atmel serial flash */
50 CHIPC_QSFLASH_ST = 4, /**< ST quad-SPI flash */
51 CHIPC_QSFLASH_AT = 5, /**< Atmel quad-SPI flash */
[all …]
|
| H A D | chipc_slicer.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
35 * The first supported FW is TRX-based used by Asus routers
54 #include <dev/cfi/cfi_var.h>
86 /* must be CFI flash */ in chipc_slicer_cfi()
87 if (device_get_devclass(dev) != devclass_find("cfi")) in chipc_slicer_cfi()
102 return (chipc_slicer_walk(dev, sc->sc_res, slices, nslices)); in chipc_slicer_cfi()
114 /* must be SPI-attached flash */ in chipc_slicer_spi()
134 return (chipc_slicer_walk(dev, sc->sc_flash_res, slices, nslices)); in chipc_slicer_spi()
158 /* Find FW header in flash memory with step=128Kb (0x1000) */ in chipc_slicer_walk()
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/fsl/ |
| H A D | ifc.txt | 1 Integrated Flash Controller
4 - name : Should be ifc
5 - compatible : should contain "fsl,ifc". The version of the integrated
6 flash controller can be found in the IFC_REV register at
9 - #address-cells : Should be either two or three. The first cell is the
12 - #size-cells : Either one or two, depending on how large each chipselect
14 - reg : Offset and length of the register set for the device
15 - interrupts: IFC may have one or two interrupts. If two interrupt
21 - little-endian : If this property is absent, the big-endian mode will
24 - ranges : Each range corresponds to a single chipselect, and covers
[all …]
|
| H A D | fsl,ifc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FSL/NXP Integrated Flash Controller
10 - Shawn Guo <shawnguo@kernel.org>
13 NXP's integrated flash controller (IFC) is an advanced version of the
16 external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
21 pattern: "^memory-controller@[0-9a-f]+$"
26 "#address-cells":
[all …]
|
| /freebsd/sys/contrib/device-tree/src/powerpc/ |
| H A D | sbc8548.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 /dts-v1/;
13 /include/ "sbc8548-pre.dtsi"
17 #address-cells = <2>;
18 #size-cells = <1>;
19 compatible = "simple-bus";
21 interrupt-parent = <&mpic>;
23 ranges = <0x0 0x0 0xff800000 0x00800000 /*8MB Flash*/
27 0x6 0x0 0xec000000 0x04000000>; /*64MB Flash*/
30 flash@0,0 {
[all …]
|
| H A D | sbc8548-altflash.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Configured for booting off the alternate (64MB SODIMM) flash.
14 /dts-v1/;
16 /include/ "sbc8548-pre.dtsi"
20 #address-cells = <2>;
21 #size-cells = <1>;
22 compatible = "simple-bus";
24 interrupt-parent = <&mpic>;
26 ranges = <0x0 0x0 0xfc000000 0x04000000 /*64MB Flash*/
30 0x6 0x0 0xef800000 0x00800000>; /*8MB Flash*/
[all …]
|
| H A D | media5200.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 &gpt0 { fsl,has-wdt; };
24 stdout-path = &console;
29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
64 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
68 phy-handle = <&phy0>;
72 phy0: ethernet-phy@0 {
[all …]
|
| /freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | gef_ppc9a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
40 /* flash@0,0 is a mirror of part of the memory in flash@1,0
41 flash@0,0 {
[all …]
|
| H A D | gef_sbc610.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
40 /* flash@0,0 is a mirror of part of the memory in flash@1,0
41 flash@0,0 {
[all …]
|
| H A D | gef_sbc310.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe0000000 0x08000000 // Paged Flash 0
33 2 0 0xe8000000 0x08000000 // Paged Flash 1
37 /* flash@0,0 is a mirror of part of the memory in flash@1,0
38 flash@0,0 {
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | orion5x-rd88f5182-nas.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include "orion5x-mv88f5182.dtsi"
11 compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
20 stdout-path = &uart0;
30 gpio-leds {
31 compatible = "gpio-leds";
32 pinctrl-0 = <&pmx_debug_led>;
[all …]
|
| /freebsd/sys/contrib/device-tree/src/xtensa/ |
| H A D | xtfpga-flash-4m.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 flash: flash@08000000 { label
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "cfi-flash";
9 bank-width = <2>;
10 device-width = <2>;
|
| H A D | xtfpga-flash-128m.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 flash: flash@00000000 { label
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "cfi-flash";
9 bank-width = <2>;
10 device-width = <2>;
|
| H A D | xtfpga-flash-16m.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 flash: flash@08000000 { label
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "cfi-flash";
9 bank-width = <2>;
10 device-width = <2>;
|
| /freebsd/sys/contrib/device-tree/src/arm/intel/ixp/ |
| H A D | intel-ixp46x-ixdp465.dts | 1 // SPDX-License-Identifier: ISC
7 /dts-v1/;
9 #include "intel-ixp45x-ixp46x.dtsi"
10 #include "intel-ixp4xx-reference-design.dtsi"
11 #include <dt-bindings/input/input.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
21 flash@0,0 {
22 compatible = "intel,ixp4xx-flash", "cfi-flash";
23 bank-width = <2>;
[all …]
|