14ad7e9b0SAdrian Chadd /*- 2*4d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 36e778a7eSPedro F. Giffuni * 44ad7e9b0SAdrian Chadd * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 54ad7e9b0SAdrian Chadd * All rights reserved. 64ad7e9b0SAdrian Chadd * 74ad7e9b0SAdrian Chadd * Redistribution and use in source and binary forms, with or without 84ad7e9b0SAdrian Chadd * modification, are permitted provided that the following conditions 94ad7e9b0SAdrian Chadd * are met: 104ad7e9b0SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 114ad7e9b0SAdrian Chadd * notice, this list of conditions and the following disclaimer, 124ad7e9b0SAdrian Chadd * without modification. 134ad7e9b0SAdrian Chadd * 2. Redistributions in binary form must reproduce at minimum a disclaimer 144ad7e9b0SAdrian Chadd * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 154ad7e9b0SAdrian Chadd * redistribution must be conditioned upon including a substantially 164ad7e9b0SAdrian Chadd * similar Disclaimer requirement for further binary redistribution. 174ad7e9b0SAdrian Chadd * 184ad7e9b0SAdrian Chadd * NO WARRANTY 194ad7e9b0SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 204ad7e9b0SAdrian Chadd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 214ad7e9b0SAdrian Chadd * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 224ad7e9b0SAdrian Chadd * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 234ad7e9b0SAdrian Chadd * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 244ad7e9b0SAdrian Chadd * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 254ad7e9b0SAdrian Chadd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 264ad7e9b0SAdrian Chadd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 274ad7e9b0SAdrian Chadd * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 284ad7e9b0SAdrian Chadd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 294ad7e9b0SAdrian Chadd * THE POSSIBILITY OF SUCH DAMAGES. 304ad7e9b0SAdrian Chadd * 314ad7e9b0SAdrian Chadd */ 324ad7e9b0SAdrian Chadd 334ad7e9b0SAdrian Chadd #ifndef _BHND_CORES_CHIPC_CHIPC_H_ 344ad7e9b0SAdrian Chadd #define _BHND_CORES_CHIPC_CHIPC_H_ 354ad7e9b0SAdrian Chadd 364ad7e9b0SAdrian Chadd #include <dev/bhnd/bhnd.h> 374ad7e9b0SAdrian Chadd #include <dev/bhnd/nvram/bhnd_nvram.h> 384ad7e9b0SAdrian Chadd 394ad7e9b0SAdrian Chadd #include "bhnd_chipc_if.h" 404ad7e9b0SAdrian Chadd 41f90f4b65SLandon J. Fuller /** 42f90f4b65SLandon J. Fuller * Supported ChipCommon flash types. 43f90f4b65SLandon J. Fuller */ 44f90f4b65SLandon J. Fuller typedef enum { 45f90f4b65SLandon J. Fuller CHIPC_FLASH_NONE = 0, /**< No flash, or a type unrecognized 46f90f4b65SLandon J. Fuller by the ChipCommon driver */ 47f90f4b65SLandon J. Fuller CHIPC_PFLASH_CFI = 1, /**< CFI-compatible parallel flash */ 48f90f4b65SLandon J. Fuller CHIPC_SFLASH_ST = 2, /**< ST serial flash */ 49f90f4b65SLandon J. Fuller CHIPC_SFLASH_AT = 3, /**< Atmel serial flash */ 50f90f4b65SLandon J. Fuller CHIPC_QSFLASH_ST = 4, /**< ST quad-SPI flash */ 51f90f4b65SLandon J. Fuller CHIPC_QSFLASH_AT = 5, /**< Atmel quad-SPI flash */ 52f90f4b65SLandon J. Fuller CHIPC_NFLASH = 6, /**< NAND flash */ 53f90f4b65SLandon J. Fuller CHIPC_NFLASH_4706 = 7 /**< BCM4706 NAND flash */ 54f90f4b65SLandon J. Fuller } chipc_flash; 55f90f4b65SLandon J. Fuller 56f90f4b65SLandon J. Fuller /** 57f90f4b65SLandon J. Fuller * ChipCommon capability flags; 58f90f4b65SLandon J. Fuller */ 59f90f4b65SLandon J. Fuller struct chipc_caps { 60f90f4b65SLandon J. Fuller uint8_t num_uarts; /**< Number of attached UARTS (1-3) */ 61f90f4b65SLandon J. Fuller bool mipseb; /**< MIPS is big-endian */ 62f90f4b65SLandon J. Fuller uint8_t uart_clock; /**< UART clock source (see CHIPC_CAP_UCLKSEL_*) */ 63f90f4b65SLandon J. Fuller uint8_t uart_gpio; /**< UARTs own GPIO pins 12-15 */ 64f90f4b65SLandon J. Fuller 65f90f4b65SLandon J. Fuller uint8_t extbus_type; /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */ 66f90f4b65SLandon J. Fuller 67f90f4b65SLandon J. Fuller chipc_flash flash_type; /**< flash type */ 68f90f4b65SLandon J. Fuller uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI 69f90f4b65SLandon J. Fuller not present */ 70f90f4b65SLandon J. Fuller 71f90f4b65SLandon J. Fuller bhnd_nvram_src nvram_src; /**< identified NVRAM source */ 72f90f4b65SLandon J. Fuller bus_size_t sprom_offset; /**< Offset to SPROM data within 73f90f4b65SLandon J. Fuller SPROM/OTP, 0 if unknown or not 74f90f4b65SLandon J. Fuller present */ 75f90f4b65SLandon J. Fuller uint8_t otp_size; /**< OTP (row?) size, 0 if not present */ 76f90f4b65SLandon J. Fuller 77f90f4b65SLandon J. Fuller uint8_t pll_type; /**< PLL type */ 78f90f4b65SLandon J. Fuller bool pwr_ctrl; /**< Power/clock control available */ 79f90f4b65SLandon J. Fuller bool jtag_master; /**< JTAG Master present */ 80f90f4b65SLandon J. Fuller bool boot_rom; /**< Internal boot ROM is active */ 81f90f4b65SLandon J. Fuller uint8_t backplane_64; /**< Backplane supports 64-bit addressing. 82f90f4b65SLandon J. Fuller Note that this does not gaurantee 83f90f4b65SLandon J. Fuller the CPU itself supports 64-bit 84f90f4b65SLandon J. Fuller addressing. */ 85f90f4b65SLandon J. Fuller bool pmu; /**< PMU is present. */ 86f90f4b65SLandon J. Fuller bool eci; /**< ECI (enhanced coexistence inteface) is present. */ 87f90f4b65SLandon J. Fuller bool seci; /**< SECI (serial ECI) is present */ 88f90f4b65SLandon J. Fuller bool sprom; /**< SPROM is present */ 89f90f4b65SLandon J. Fuller bool gsio; /**< GSIO (SPI/I2C) present */ 90f90f4b65SLandon J. Fuller bool aob; /**< AOB (always on bus) present. 91f90f4b65SLandon J. Fuller If set, PMU and GCI registers are 92f90f4b65SLandon J. Fuller not accessible via ChipCommon, 93f90f4b65SLandon J. Fuller and are instead accessible via 94f90f4b65SLandon J. Fuller dedicated cores on the bhnd bus */ 95f90f4b65SLandon J. Fuller }; 96f90f4b65SLandon J. Fuller 974ad7e9b0SAdrian Chadd #endif /* _BHND_CORES_CHIPC_CHIPC_H_ */ 98