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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Drate.c46 {6500, 13500, CEIL(6500 * 10, 9), CEIL(13500 * 10, 9), 0x00,
49 {13000, 27000, CEIL(13000 * 10, 9), CEIL(27000 * 10, 9), 0x08,
52 {19500, 40500, CEIL(19500 * 10, 9), CEIL(40500 * 10, 9), 0x0A,
55 {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0x10,
58 {39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x12,
61 {52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0x19,
64 {58500, 121500, CEIL(58500 * 10, 9), CEIL(121500 * 10, 9), 0x1A,
67 {65000, 135000, CEIL(65000 * 10, 9), CEIL(135000 * 10, 9), 0x1C,
70 {13000, 27000, CEIL(13000 * 10, 9), CEIL(27000 * 10, 9), 0x40,
73 {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0x48,
[all …]
/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
H A Dhtb.json102 … "matchPattern": "class htb 1:1 root prio 0 rate 20Kbit ceil 20Kbit burst 1000b cburst 1600b",
124 … "matchPattern": "class htb 1:1 root prio 0 rate 20Kbit ceil 20Kbit burst 1600b cburst 1600b",
146 … "matchPattern": "class htb 1:1 root prio 1 rate 20Kbit ceil 20Kbit burst 1600b cburst 1600b",
154 "name": "Create HTB with class ceil setting",
165 … "cmdUnderTest": "$TC class add dev $DUMMY parent 1: classid 1:1 htb rate 20Kbit ceil 10Kbit",
168 … "matchPattern": "class htb 1:1 root prio 0 rate 20Kbit ceil 10Kbit burst 1600b cburst 1600b",
190 … "matchPattern": "class htb 1:1 root prio 0 rate 20Kbit ceil 20Kbit burst 1600b cburst 2000b",
212 "matchPattern": "class htb 1:1 root prio 0 rate 20Kbit ceil 20Kbit burst 2Kb cburst 2Kb",
234 … "matchPattern": "class htb 1:1 root prio 0 rate 20Kbit ceil 20Kbit burst 1600b cburst 1600b",
/linux/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Dhtb.c270 qos_dbg(htb->mdev, "Convert: rate %llu, parent ceil %llu -> bw_share %u\n", in mlx5e_htb_convert_rate()
276 static void mlx5e_htb_convert_ceil(struct mlx5e_htb *htb, u64 ceil, u32 *max_average_bw) in mlx5e_htb_convert_ceil() argument
279 *max_average_bw = max_t(u32, div_u64(ceil, BYTES_IN_MBIT), 1); in mlx5e_htb_convert_ceil()
281 qos_dbg(htb->mdev, "Convert: ceil %llu -> max_average_bw %u\n", in mlx5e_htb_convert_ceil()
282 ceil, *max_average_bw); in mlx5e_htb_convert_ceil()
287 u32 parent_classid, u64 rate, u64 ceil, in mlx5e_htb_leaf_alloc_queue() argument
295 qos_dbg(htb->mdev, "TC_HTB_LEAF_ALLOC_QUEUE classid %04x, parent %04x, rate %llu, ceil %llu\n", in mlx5e_htb_leaf_alloc_queue()
296 classid, parent_classid, rate, ceil); in mlx5e_htb_leaf_alloc_queue()
314 mlx5e_htb_convert_ceil(htb, ceil, &node->max_average_bw); in mlx5e_htb_leaf_alloc_queue()
343 u64 rate, u64 ceil, struct netlink_ext_ack *extack) in mlx5e_htb_leaf_to_inner() argument
[all …]
H A Dhtb.h26 u32 parent_classid, u64 rate, u64 ceil,
30 u64 rate, u64 ceil, struct netlink_ext_ack *extack);
37 mlx5e_htb_node_modify(struct mlx5e_htb *htb, u16 classid, u64 rate, u64 ceil,
H A Dqos.c425 htb_qopt->rate, htb_qopt->ceil, htb_qopt->extack); in mlx5e_htb_setup_tc()
432 htb_qopt->rate, htb_qopt->ceil, htb_qopt->extack); in mlx5e_htb_setup_tc()
441 return mlx5e_htb_node_modify(htb, htb_qopt->classid, htb_qopt->rate, htb_qopt->ceil, in mlx5e_htb_setup_tc()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn32/
H A Ddcn32_dpp.c54 memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ in dscl32_calc_lb_num_partitions()
55 memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ in dscl32_calc_lb_num_partitions()
56 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ in dscl32_calc_lb_num_partitions()
187 memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ in dscl32_spl_calc_lb_num_partitions()
188 memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ in dscl32_spl_calc_lb_num_partitions()
189 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ in dscl32_spl_calc_lb_num_partitions()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp.c303 memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ in dscl401_calc_lb_num_partitions()
304 memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ in dscl401_calc_lb_num_partitions()
305 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ in dscl401_calc_lb_num_partitions()
378 memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ in dscl401_spl_calc_lb_num_partitions()
379 memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ in dscl401_spl_calc_lb_num_partitions()
380 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ in dscl401_spl_calc_lb_num_partitions()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp.c280 memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ in dscl2_calc_lb_num_partitions()
281 memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ in dscl2_calc_lb_num_partitions()
282 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ in dscl2_calc_lb_num_partitions()
457 memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ in dscl2_spl_calc_lb_num_partitions()
458 memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ in dscl2_spl_calc_lb_num_partitions()
459 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ in dscl2_spl_calc_lb_num_partitions()
/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h349 #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
352 #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
355 /* fua = fxtl/(16*Ceil (Div/16)) */
356 /* Tua = 16*Ceil (Div/16)*Txtl */
488 #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
491 #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
494 /* fsd = fxtl/(16*Ceil (Div/16)) */
495 /* Tsd = 16*Ceil (Div/16)*Txtl */
646 #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \
648 /* faud = fmc/(32*Ceil (Div/32)) */
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dqos.c119 maxrate = (node->rate > node->ceil) ? node->rate : node->ceil; in otx2_config_sched_shaping()
475 txschq_node->ceil = 0; in otx2_qos_alloc_txschq_node()
505 u16 classid, u32 prio, u64 rate, u64 ceil, in otx2_qos_sw_create_leaf_node() argument
521 node->ceil = otx2_convert_rate(ceil); in otx2_qos_sw_create_leaf_node()
1223 u32 parent_classid, u64 rate, u64 ceil, in otx2_qos_leaf_alloc_queue() argument
1233 …"TC_HTB_LEAF_ALLOC_QUEUE: classid=0x%x parent_classid=0x%x rate=%lld ceil=%lld prio=%lld quantum=%… in otx2_qos_leaf_alloc_queue()
1234 classid, parent_classid, rate, ceil, prio, quantum); in otx2_qos_leaf_alloc_queue()
1303 ceil, quantum, qid, static_cfg); in otx2_qos_leaf_alloc_queue()
1362 u16 child_classid, u64 rate, u64 ceil, u64 prio, in otx2_qos_leaf_to_inner() argument
1372 "TC_HTB_LEAF_TO_INNER classid %04x, child %04x, rate %llu, ceil %llu\n", in otx2_qos_leaf_to_inner()
[all …]
H A Dqos.h60 u64 ceil; member
/linux/fs/bcachefs/
H A Dutil.c653 u64 bch2_get_random_u64_below(u64 ceil) in bch2_get_random_u64_below() argument
655 if (ceil <= U32_MAX) in bch2_get_random_u64_below()
656 return __get_random_u32_below(ceil); in bch2_get_random_u64_below()
660 u64 mult = ceil * rand; in bch2_get_random_u64_below()
662 if (unlikely(mult < ceil)) { in bch2_get_random_u64_below()
664 div64_u64_rem(-ceil, ceil, &bound); in bch2_get_random_u64_below()
667 mult = ceil * rand; in bch2_get_random_u64_below()
671 return mul_u64_u64_shr(ceil, rand, 64); in bch2_get_random_u64_below()
/linux/lib/math/
H A Dreciprocal_div.c41 /* ceil(log2(d)) */ in reciprocal_value_adv()
48 "ceil(log2(0x%08x)) == 32, %s doesn't support such divisor", in reciprocal_value_adv()
/linux/net/sched/
H A Dsch_htb.c97 struct psched_ratecfg ceil; member
677 toks -= (s64) psched_l2t_ns(&cl->ceil, bytes); in htb_accnt_ctokens()
692 * borrowing from "level". It accounts bytes to ceil leaky bucket for
1265 psched_ratecfg_getrate(&opt.ceil, &cl->ceil); in htb_dump_class()
1278 if ((cl->ceil.rate_bytes_ps >= (1ULL << 32)) && in htb_dump_class()
1279 nla_put_u64_64bit(skb, TCA_HTB_CEIL64, cl->ceil.rate_bytes_ps, in htb_dump_class()
1789 if (!hopt->rate.rate || !hopt->ceil.rate) in htb_change_class()
1794 if (hopt->rate.overhead || hopt->ceil.overhead) { in htb_change_class()
1798 if (hopt->rate.mpu || hopt->ceil.mpu) { in htb_change_class()
1809 if (hopt->ceil.linklayer == TC_LINKLAYER_UNAWARE) in htb_change_class()
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/linux/drivers/char/
H A Drandom.c191 * u32 get_random_u32_below(u32 ceil)
193 * u32 get_random_u32_inclusive(u32 floor, u32 ceil)
557 u32 __get_random_u32_below(u32 ceil) in DEFINE_BATCHED_ENTROPY()
560 * This is the slow path for variable ceil. It is still fast, most of in DEFINE_BATCHED_ENTROPY()
562 * opportunistically comparing the lower half to ceil itself, before in DEFINE_BATCHED_ENTROPY()
564 * whose lower half would indicate a range indivisible by ceil. The use in DEFINE_BATCHED_ENTROPY()
565 * of `-ceil % ceil` is analogous to `2^32 % ceil`, but is computable in DEFINE_BATCHED_ENTROPY()
572 * This function is technically undefined for ceil == 0, and in fact in DEFINE_BATCHED_ENTROPY()
579 if (unlikely(!ceil)) in DEFINE_BATCHED_ENTROPY()
582 mult = (u64)ceil * rand; in DEFINE_BATCHED_ENTROPY()
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/linux/drivers/iio/light/
H A Dlv0104cs.c278 int floor, ceil, mid; in lv0104cs_set_calibscale() local
285 ceil = lv0104cs_calibscales[i + 1].val * 1000000 in lv0104cs_set_calibscale()
287 mid = (floor + ceil) / 2; in lv0104cs_set_calibscale()
296 if (calibscale >= mid && calibscale <= ceil) { in lv0104cs_set_calibscale()
/linux/drivers/clk/tegra/
H A Dclk-device.c47 dev_dbg(dev, "failed to find ceil OPP for %luHz\n", rate); in tegra_clock_set_pd_state()
140 * state. For some clocks common OPP helper may fail to find ceil in tegra_clock_probe()
/linux/drivers/media/platform/ti/omap3isp/
H A Dispcsiphy.c223 /* THS_TERM: Programmed value = ceil(12.5 ns/DDRClk period) - 1. */ in omap3isp_csiphy_config()
226 /* THS_SETTLE: Programmed value = ceil(90 ns/DDRClk period) + 3. */ in omap3isp_csiphy_config()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_dscl.c413 memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */ in dpp1_dscl_calc_lb_num_partitions()
414 memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */ in dpp1_dscl_calc_lb_num_partitions()
415 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ in dpp1_dscl_calc_lb_num_partitions()
/linux/include/linux/
H A Dreciprocal_div.h47 * ceil(log2(d)) result will be 32 which then requires u128 divide on host. The
/linux/drivers/net/ethernet/sfc/siena/
H A Drx_common.h17 /* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */
/linux/drivers/net/ethernet/sfc/
H A Drx_common.h17 /* Each packet can consume up to ceil(max_frame_len / buffer_size) buffers */
/linux/Documentation/devicetree/bindings/ptp/
H A Dfsl,ptp.yaml94 tmr_add = ceil(2^32 / FreqDivRatio)
/linux/drivers/ufs/host/
H A Dufs-qcom.c1376 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will in ufs_qcom_set_clk_40ns_cycles()
1377 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware in ufs_qcom_set_clk_40ns_cycles()
1433 cycles_in_1us = ceil(clk_freq, HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
1447 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
1452 cycles_in_1us = ceil(clki->max_freq, HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
1454 cycles_in_1us = ceil(clk_get_rate(clki->clk), HZ_PER_MHZ); in ufs_qcom_set_core_clk_ctrl()
/linux/rust/kernel/
H A Dopp.rs285 Ceil, enumerator
873 SearchType::Ceil => unsafe { in opp_from_freq()
899 SearchType::Ceil => unsafe { in opp_from_level()
924 SearchType::Ceil => unsafe { in opp_from_bw()

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