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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcci.txt2 ARM CCI cache coherent interconnect binding description
5 ARM multi-cluster systems maintain intra-cluster coherency through a
6 cache coherent interconnect (CCI) that is capable of monitoring bus
10 clusters, through memory mapped interface, with a global control register
11 space and multiple sets of interface control registers, one per slave
14 * CCI interconnect node
16 Description: Describes a CCI cache coherent Interconnect component
18 Node name must be "cci".
20 through the CCI interconnect is the same as the one seen from the
22 Every CCI node has to define the following properties:
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H A Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM CCI Cache Coherent Interconnect
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
14 coherent interconnect (CCI) that is capable of monitoring bus transactions
18 clusters, through memory mapped interface, with a global control register
19 space and multiple sets of interface control registers, one per slave
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H A Dcci-control-port.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CCI Interconnect Bus Masters
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 Masters in the device tree connected to a CCI port (inclusive of CPUs
19 cci-control-port:
25 - |
27 #address-cells = <1>;
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
58 compatible = "arm,cortex-a7";
61 clock-frequency = <1000000000>;
62 cci-control-port = <&cci_control0>;
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H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
59 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
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H A Dexynos5260.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos5260-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
37 cpu-map {
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/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6795.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-binding
450 cci: cci@10390000 { global() label
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H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
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/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Dqcom,i2c-cci.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Camera Control Interface (CCI) I2C controller
10 - Loic Poulain <loic.poulain@linaro.org>
11 - Robert Foss <robert.foss@linaro.org>
16 - enum:
17 - qcom,msm8226-cci
18 - qcom,msm8974-cci
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/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
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H A Dsun8i-a83t.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 #include <dt-bindings/thermal/thermal.h>
56 interrupt-parent = <&gic>;
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/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7629.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dov5647.txt2 ---------------------------------
4 OV5647 is a raw image sensor with MIPI CSI-2 and CCP2 image data interfaces
5 and CCI (I2C compatible) control bus.
9 - compatible : "ovti,ov5647".
10 - reg : I2C slave address of the sensor.
11 - clocks : Reference to the xclk clock.
13 The common video interfaces bindings (see video-interfaces.txt) should be
15 node should contain one 'port' child node with an 'endpoint' subnode.
19 - remote-endpoint: A phandle to the bus receiver's endpoint node.
29 port {
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H A Dovti,ov5647.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
11 - Jacopo Mondi <jacopo@jmondi.org>
13 description: |-
14 The OV5647 is a raw image sensor with MIPI CSI-2 and CCP2 image data
15 interfaces and CCI (I2C compatible) control bus.
29 pwdn-gpios:
33 port:
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H A Dov5647.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
11 - Jacopo Mondi <jacopo@jmondi.org>
13 description: |-
14 The OV5647 is a raw image sensor with MIPI CSI-2 and CCP2 image data
15 interfaces and CCI (I2C compatible) control bus.
29 pwdn-gpios:
33 port:
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H A Dgalaxycore,gc08a3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: GalaxyCore gc08a3 1/4" 8M Pixel MIPI CSI-2 sensor
11 - Zhi Mao <zhi.mao@mediatek.com>
14 The gc08a3 is a raw image sensor with an MIPI CSI-2 image data
15 interface and CCI (I2C compatible) control bus. The output format
28 dovdd-supply: true
30 avdd-supply: true
32 dvdd-supply: true
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H A Dgalaxycore,gc05a2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: GalaxyCore gc05a2 1/5" 5M Pixel MIPI CSI-2 sensor
11 - Zhi Mao <zhi.mao@mediatek.com>
14 The gc05a2 is a raw image sensor with an MIPI CSI-2 image data
15 interface and CCI (I2C compatible) control bus. The output format
28 dovdd-supply: true
30 avdd-supply: true
32 dvdd-supply: true
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H A Dsamsung,s5k6a3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13 S5K6A3(YX) is a raw image sensor with MIPI CSI-2 and CCP2 image data
14 interfaces and CCI (I2C compatible) control bus.
26 clock-names:
28 - const: extclk
30 clock-frequency:
38 afvdd-supply:
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H A Dhynix,hi846.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dsamsung-s5k6a3.txt2 ---------------------------------
4 S5K6A3(YX) is a raw image sensor with MIPI CSI-2 and CCP2 image data interfaces
5 and CCI (I2C compatible) control bus.
9 - compatible : "samsung,s5k6a3";
10 - reg : I2C slave address of the sensor;
11 - svdda-supply : core voltage supply;
12 - svddio-supply : I/O voltage supply;
13 - afvdd-supply : AF (actuator) voltage supply;
14 - gpios : specifier of a GPIO connected to the RESET pin;
15 - clocks : should contain list of phandle and clock specifier pairs
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/freebsd/share/doc/papers/beyond4.3/
H A Dbeyond43.ms28 .\" *troff -ms
34 of Berkeley\s-2\fP
68 The fifth is to evaluate alternate access control mechanisms and
71 Other areas of work include multi-architecture support,
90 Multi-architecture support
96 non-VAX processor, the CCI Power 6/32 and 6/32SX. (This addition also
98 Harris HCX-7 and HCX-9, as well as the Sperry 7000/40 and ICL machines.)
100 device drivers done for CCI's 4.2BSD UNIX,
102 The entire source tree, including all kernel and user-level sources,
115 patterns in the UNIX kernel and a hybrid strategy that is time-efficient
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmediatek,net.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc8280xp.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
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/freebsd/share/doc/smm/01.setup/
H A D4.t67 tty terminal handling and job control
75 lfs log-based filesystem
77 nfs Sun-compatible network filesystem
80 fdesc access to per-process file descriptors
95 netiso ISO protocols (TP-4, CLNP, CLTP, etc)
103 hp300 HP 9000/300 series of Motorola 68000-based machines
104 hp code common to both HP 68k and (non-existent) PA-RISC ports
105 i386 Intel 386/486-based PC machines
106 luna68k Omron 68000-based workstations
107 news3400 Sony News MIPS-based workstations
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