| /linux/Documentation/hwmon/ |
| H A D | ibmpowernv.rst | 11 -----------
22 the DT maps to an attribute file in 'sysfs'. The node exports unique 'sensor-id'
26 -----------
28 CONFIG_SENSORS_IBMPOWERNV. It can also be built as module 'ibmpowernv'.
31 ----------------
36 fanX_fault - 0: No fail condition
37 - 1: Failing fan
43 tempX_enable Enable/disable all temperature sensors belonging to the
44 sub-group. In POWER9, this attribute corresponds to
45 each OCC. Using this attribute each OCC can be asked to
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| /linux/Documentation/admin-guide/ |
| H A D | kernel-parameters.txt | 9 accept_memory=eager can be used to accept all memory
16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nocmcff -- Disable firmware first mode for corrected
28 nospcr -- disable console in ACPI SPCR table as
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| /linux/Documentation/ABI/stable/ |
| H A D | sysfs-driver-firmware-zynqmp | 1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
8 Global general storage register that can be used
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
35 can be used by system to pass information between
38 This register is only reset by the power-on reset
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| /linux/Documentation/driver-api/crypto/iaa/ |
| H A D | iaa-crypto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 The IAA hardware spec can be found here:
18 higher-level compression devices such as zswap.
20 Users can select IAA compress/decompress acceleration by specifying
24 For example, a zswap device can select the IAA 'fixed' mode
25 represented by selecting the 'deflate-iaa' crypto compression
28 # echo deflate-iaa > /sys/module/zswap/parameters/compressor
38 'deflate-iaa'. (Because the IAA hardware has a 4k history-window
52 Cryptographic API -> Hardware crypto devices -> Support for Intel(R) IAA Compression Accelerator
59 …Cryptographic API -> Hardware crypto devices -> Support for Intel(R) IAA Compression -> Enable Int…
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | sprd,pinctrl.txt | 9 driving level": One pin can output 3.0v or 1.8v, depending on the
11 select 3.0v, then the pin can output 3.0v. "system control" is used
15 There are too much various configuration that we can not list all
16 of them, so we can not make every Spreadtrum-special configuration
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
40 - bias-pull-down
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| H A D | mediatek,mt8195-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
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| H A D | thead,th1520-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-Head TH1520 SoC pin controller
10 - Emil Renner Berthing <emil.renner.berthing@canonical.com>
13 Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC.
17 PADCTRL_AOSYS -> PAD Group 1
18 PADCTRL1_APSYS -> PAD Group 2
19 PADCTRL0_APSYS -> PAD Group 3
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| H A D | mediatek,mt8188-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui Liu <hui.liu@mediatek.com>
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
25 are defined in <dt-bindings/gpio/gpio.h>.
28 gpio-ranges:
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| H A D | mediatek,mt8186-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
31 gpio-line-names: true
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| H A D | mediatek,mt8196-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8196-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lei Xue <lei.xue@mediatek.com>
11 - Cathy Xu <ot_cathy.xu@mediatek.com>
18 const: mediatek,mt8196-pinctrl
22 - description: gpio base
23 - description: rt group IO
24 - description: rm1 group IO
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| H A D | mediatek,mt8189-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8189-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lei Xue <lei.xue@mediatek.com>
11 - Cathy Xu <ot_cathy.xu@mediatek.com>
18 const: mediatek,mt8189-pinctrl
22 - description: gpio base
23 - description: lm group IO
24 - description: rb0 group IO
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| H A D | starfive,jh7110-sys-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
13 can be multiplexed and have configurable bias, drive strength,
18 any GPIO can be set up to be controlled by any of the peripherals.
21 - Hal Feng <hal.feng@starfivetech.com>
25 const: starfive,jh7110-sys-pinctrl
39 interrupt-controller: true
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | snps,dwc3-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
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| /linux/arch/arm64/include/asm/ |
| H A D | el2_setup.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
11 #error Assembly-only header
17 #include <linux/irqchip/arm-gic-v3.h>
23 * Compliant CPUs advertise their VHE-onlyness with
25 * can reset into an UNKNOWN state and might not read as 1 until it has
27 * Initalize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H
36 * Unfortunately, HCR_EL2.E2H can be RES1 even if not advertised
39 * - Fruity CPUs predate the !FEAT_E2H0 relaxation, and seem to
42 * - On CPUs that lack FEAT_FGT, a hypervisor can't trap guest
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| /linux/Documentation/trace/coresight/ |
| H A D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
13 debug module and it is mainly used for two modes: self-hosted debug and
15 debugger connects with SoC from JTAG port; on the other hand the program can
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
22 debug mechanism, Linux kernel can access these related registers from mmio
29 --------------
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| /linux/Documentation/driver-api/nvdimm/ |
| H A D | security.rst | 6 ---------------
10 security DSMs: "get security state", "set passphrase", "disable passphrase",
16 ------------------
28 update <old_keyid> <new_keyid> - enable or update passphrase.
29 disable <keyid> - disable enabled security and remove key.
30 freeze - freeze changing of security states.
31 erase <keyid> - delete existing user encryption key.
32 overwrite <keyid> - wipe the entire nvdimm.
33 master_update <keyid> <new_keyid> - enable or update master passphrase.
34 master_erase <keyid> - delete existing user encryption key.
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| /linux/Documentation/fb/ |
| H A D | viafb.rst | 6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
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| /linux/Documentation/sound/ |
| H A D | alsa-configuration.rst | 2 Advanced Linux Sound Architecture - Driver Configuration guide
10 primary sound card support (``CONFIG_SOUND``). Since ALSA can emulate
32 The user can load modules with options. If the module supports more than
33 one card and you have more than one card of the same type then you can
38 ----------
47 limiting card index for auto-loading (1-8);
49 For auto-loading more than one card, specify this option
50 together with snd-card-X aliases.
57 (0 = disable debug prints, 1 = normal debug messages,
60 This option can be dynamically changed via sysfs
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| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | gather_data_sampling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 GDS - Gather Data Sampling
10 -------
17 attacks. GDS is a purely sampling-based attack.
24 Because the buffers are shared between Hyper-Threads cross Hyper-Thread attacks
28 ----------------
29 Without mitigation, GDS can infer stale data across virtually all
32 Non-enclaves can infer SGX enclave data
33 Userspace can infer kernel data
34 Guests can infer data from hosts
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| /linux/Documentation/networking/device_drivers/ethernet/intel/ |
| H A D | ice.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2018-2021 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Important Notes
16 - Additional Features & Configurations
17 - Performance Optimization
22 Driver information can be obtained using ethtool and lspci.
28 This driver supports XDP (Express Data Path) and AF_XDP zero-copy. Note that
43 -------------------------------------------
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| /linux/arch/arm/boot/dts/microchip/ |
| H A D | at91-sama5d2_xplained.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board
8 /dts-v1/;
10 #include "sama5d2-pinfunc.h"
11 #include <dt-bindings/mfd/atmel-flexcom.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/regulator/active-semi,8945a-regulator.h>
18 compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5";
28 stdout-path = "serial0:115200n8";
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| /linux/Documentation/PCI/ |
| H A D | pci-iov-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Yu Zhao <yu.zhao@intel.com>
10 - Donald Dutile <ddutile@redhat.com>
15 What is SR-IOV
16 --------------
18 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
22 Allocation of the VF can be dynamically controlled by the PF via
25 turned on, each VF's PCI configuration space can be accessed by its own
28 operates on the register set so it can be functional and appear as a
34 How can I enable SR-IOV capability
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| /linux/drivers/irqchip/ |
| H A D | irq-bcm2835.c | 1 // SPDX-License-Identifier: GPL-2.0+
16 * Quirk 2: You can't mask the register 1/2 pending interrupts
20 * You can mask the interrupts and get on with things. With this controller
21 * you can't do that.
23 * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
25 * Those interrupts that have shortcuts can only be masked/unmasked in
26 * their respective banks' enable/disable registers. Doing so in the bank 0
27 * enable/disable registers has no effect.
30 * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
54 /* Shortcuts can't be disabled so any unknown new ones need to be masked */
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|
| /linux/Documentation/filesystems/ |
| H A D | f2fs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Flash-Friendly File System (F2FS)
10 NAND flash memory-based storage devices, such as SSD, eMMC, and SD cards, have
16 F2FS is a file system exploiting NAND flash memory-based storage devices, which
17 is based on Log-structured File System (LFS). The design has been focused on
21 Since a NAND flash memory-based storage device shows different characteristic
23 F2FS and its tools support various parameters not only for configuring on-disk
29 - git://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs-tools.git
33 - linux-f2fs-devel@lists.sourceforge.net
37 - https://bugzilla.kernel.org/enter_bug.cgi?product=File%20System&component=f2fs
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| /linux/Documentation/ABI/testing/ |
| H A D | rtc-cdev | 4 Contact: linux-rtc@vger.kernel.org
6 The ioctl interface to drivers for real-time clocks (RTCs).
13 * RTC_AIE_ON, RTC_AIE_OFF: Enable or disable the alarm interrupt
17 RTCs that support alarms. Can be set upto 24 hours in the
22 powerful interface, which can issue alarms beyond 24 hours and
25 * RTC_PIE_ON, RTC_PIE_OFF: Enable or disable the periodic
28 * RTC_UIE_ON, RTC_UIE_OFF: Enable or disable the update
48 newer features -- including those enabled by ACPI -- are exposed
49 by the RTC class framework, but can't be supported by the older
|