| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
6 can be accessed at any given time via four chip selects with 64M byte access
7 per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
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| H A D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
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| H A D | arm,pl35x-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
20 # We need a select here so we don't match all nodes with 'arm,primecell'
21 select:
26 - arm,pl353-smc-r2p1
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| H A D | arm,pl353-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM PL353 Static Memory Controller (SMC) device-tree bindings
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
14 The PL353 Static Memory Controller is a bus where you can connect two kinds
18 # We need a select here so we don't match all nodes with 'arm,primecell'
19 select:
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| H A D | omap-gpmc.txt | 7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | micrel.txt | 7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
32 actually select a mode.
34 - clocks, clock-names: contains clocks according to the common clock bindings.
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
38 input clock. Used to determine the XI input clock.
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | nvidia,tegra20-gmi.txt | 4 external memory. Can be used to attach various high speed devices such as
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ti/ |
| H A D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
9 In order to provide the support for ATL and its output clocks (which can be used
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | qcom,spi-qup.txt | 4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
19 - clock-names: Should be "core" for the core clock and "iface" for the
20 AHB clock.
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| H A D | brcm,bcm63xx-hsspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
19 brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to
20 use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as
23 This rev 1.0 controller has a limitation that can not keep the chip select line
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| /freebsd/contrib/ntp/html/ |
| H A D | prefer.html | 1 <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
13 <!-- #BeginDate format:En2m -->10-Mar-2014 05:18<!-- #EndDate -->
22 <li class="inline"><a href="#clockhop">3. Anti-Clockhop Algorithm</a></li>
30 … for choosing from among the survivors of the clock cluster algorithm a set of contributors to t…
31 …ces</em> and mobilizes an association for each source found. These sources can result from explici…
32 …select.html">Clock Select Algorithm</a> page and to determine the <em>truechimers</em> from among …
33 …clock. The mitigation rules select from among the survivors a <em>system peer</em> from which a se…
35 …clock combine algorithm uses the survivor list to produce a weighted average of both offset and ji…
36 <p> The clock combine algorithm uses a weight factor for each survivor equal to the reciprocal of t…
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| H A D | stats.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
12 <!-- #BeginDate format:En2m -->26-Jul-2015 06:29<!-- #EndDate -->
28 …<li>Nominal estimate of the server clock time relative to the client clock time. This is called <e…
29 …<li>Roundtrip system and network delay measured by the on-wire protocol. This is call <em>roundtri…
30 …<li>Potential clock offset error due to the maximum uncorrected system clock frequency error. This…
31 …<li>Expected error, consisting of the root mean square (RMS) nominal clock offset sample differenc…
38 …y the on-wire protocol, as described below. The algorithms of the box labeled Selection and Combin…
40 …-wire protocol, as described on the <a href="warp.html">How NTP Works</a> page. In addition, the d…
42 …ote. In very fast networks where the client clock frequency is not within 1 PPM or so of the the s…
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| H A D | cluster.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
6 <title>Clock Cluster Algorithm</title>
11 <h3>Clock Cluster Algorithm</h3>
13 <!-- #BeginDate format:En2m -->15-Nov-2012 06:02<!-- #EndDate -->
16 …clock cluster algorithm processes the truechimers produced by the clock select algorithm to produc…
17 …. For the <em>i</em>th candidate on the list, a statistic called the <em>select jitter</em> relati…
21 …clock filter algorithm. The metric used by the cluster algorithm is the select jitter φ<sub>S<…
22 …select jitter must be recomputed at each round, but the peer jitter does not change. At each round…
23 …d, the pruning process terminates. The<tt> minclock</tt> default is 3, but can be changed to fit …
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| H A D | select.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
6 <title>Clock Select Algorithm</title>
11 <h3>Clock Select Algorithm</h3>
13 <!-- #BeginDate format:En2m -->10-Mar-2014 05:22<!-- #EndDate -->
16 …clock select algorithm determines from a set of sources , which are correct (<em>truechimers</em>)…
21 …<li>A <em>loop</em> <em>error</em> occurs if the source is synchronized to the client. This can oc…
29 … interval can represent the true time; however, as shown below, this may throw away valuable stati…
31 …can contribute to the final outcome; that is, they are truechimers. Samples in the intersection in…
33 <p>Figure 2. Clock Select Algorithm</p>
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | adi,ad7124.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stefan Popa <stefan.popa@analog.com>
14 Bindings for the Analog Devices AD7124 ADC device. Datasheet can be
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7124-8.pdf
21 - adi,ad7124-4
22 - adi,ad7124-8
25 description: SPI chip select number for the device
30 description: phandle to the master clock (mclk)
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| H A D | adi,ad4130.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Cosmin Tanislav <cosmin.tanislav@analog.com>
14 Bindings for the Analog Devices AD4130 ADC. Datasheet can be found here:
15 https://www.analog.com/media/en/technical-documentation/data-sheets/AD4130-8.pdf
20 - adi,ad4130
27 description: phandle to the master clock (mclk)
29 clock-names:
31 - const: mclk
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| H A D | adi,ad7173.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ceclan Dumitru <dumitru.ceclan@analog.com>
15 The AD717x family offer a complete integrated Sigma-Delta ADC solution which
16 can be used in high precision, low noise single channel applications
18 (Factory Automation PLC Input modules). The Sigma-Delta ADC is intended
23 The AD411X family encompasses a series of low power, low noise, 24-bit,
24 sigma-delta analog-to-digital converters that offer a versatile range of
26 fully differential/single-ended and bipolar voltage inputs.
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| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | fsl-flexcan.txt | 1 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
5 - compatible : Should be "fsl,<processor>-flexcan"
10 - fsl,p1010-flexcan
12 - reg : Offset and length of the register set for this device
13 - interrupts : Interrupt tuple for this device
17 - clock-frequency : The oscillator frequency driving the flexcan device
19 - xceiver-supply: Regulator that powers the CAN transceiver
21 - big-endian: This means the registers of FlexCAN controller are big endian.
27 - fsl,stop-mode: register bits of stop mode control, the format is
30 req_gpr is the gpr register offset of CAN stop request.
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| H A D | rcar_can.txt | 1 Renesas R-Car CAN controller Device Tree Bindings
2 -------------------------------------------------
5 - compatible: "renesas,can-r8a7742" if CAN controller is a part of R8A7742 SoC.
6 "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC.
7 "renesas,can-r8a7744" if CAN controller is a part of R8A7744 SoC.
8 "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
9 "renesas,can-r8a77470" if CAN controller is a part of R8A77470 SoC.
10 "renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC.
11 "renesas,can-r8a774b1" if CAN controller is a part of R8A774B1 SoC.
12 "renesas,can-r8a774c0" if CAN controller is a part of R8A774C0 SoC.
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| H A D | renesas,rcar-can.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN Controller
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,can-r8a7778 # R-Car M1-A
18 - renesas,can-r8a7779 # R-Car H1
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| /freebsd/share/man/man4/ |
| H A D | snd_hdsp.4 | 35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
57 .Bl -bullet -compact
59 RME HDSP 9632 (optional AO4S-192 and AIS-192 extension boards)
69 (32kHz-48kHz) and 4 channels at double speed (64kHz-96kHz).
70 Only the HDSP 9632 can operate at quad speed (128kHz-192kHz), ADAT is
72 Depending on sample rate and channel format selected, not all pcm channels can
75 These settings can be entered at the
79 .Bl -tag -width indent
82 When opened in multi-channel audio software, this makes all ports available
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| H A D | snd_hdspe.4 | 34 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
56 .Bl -bullet -compact
58 RME HDSPe AIO (optional AO4S-192 and AI4S-192 extension boards)
68 (32kHz-48kHz), 4 channels at double speed (64kHz-96kHz), and 2 channels at
69 quad speed (128kHz-192kHz).
70 Depending on sample rate and channel format selected, not all pcm channels can
73 These settings can be entered at the
77 .Bl -tag -width indent
80 When opened in multi-channel audio software, this makes all ports available
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| H A D | spigen.4 | 36 .Bd -ragged -offset indent
45 .Bd -literal -offset indent
54 device is associated with a single chip-select
56 with that chip-select line asserted.
58 SPI data transfers are inherently bi-directional; there are no separate
75 .Bl -tag -width indent
83 .Bd -literal
91 The buffers for the transfer are a previously-mmap'd region.
100 is non-zero, the data appears in the memory region immediately
104 .Bd -literal
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| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | arm,sp804.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Haojian Zhuang <haojian.zhuang@linaro.org>
14 16 or 32 bit operation and capable of running in one-shot, periodic, or
15 free-running mode. The input clock is shared, but can be gated and prescaled
18 There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
21 # Need a custom select here or 'arm,primecell' will match on lots of nodes
22 select:
27 - arm,sp804
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_serdes_25g_regs.h | 7 Alternatively, this file can be distributed under the terms of the GNU General
8 Public License V2 or V3 as published by the Free Software Foundation and can be
9 found at http://www.gnu.org/licenses/gpl-2.0.html
132 /* Bit-wise write enable */
138 * 0x0 – Select reference clock from Bump
139 * 0x1 – Select inter-macro reference clock from the left side
141 * 0x3 – Select inter-macro reference clock from the right side
155 * 0x1 – Select reference clock from Bump
156 * 0x2 – Select inter-macro reference clock input from right side
171 * 0x1 – Select reference clock from Bump
[all …]
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