cacheable (full) in projects: linux - OpenGrok search results

Searched full:cacheable (Results 1 – 25 of 223) sorted by relevance

/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A D	cache.json	5 …transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill resp… 140 …efDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable.", 152 …iption": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable.", 206 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 212 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 218 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 224 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 230 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 236 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… 242 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A D	cache.json	70 …efDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable.", 82 …iption": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable.", 136 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 142 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 148 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 154 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 160 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 166 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… 172 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… 178 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	cache.json	70 …efDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable.", 82 …iption": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable.", 136 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 142 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 148 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 154 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 160 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 166 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… 172 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… 178 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… [all …]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	memory.json	71 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 81 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 91 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 101 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 111 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 121 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 301 …"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from… 311 …"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses… 321 …"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses… 331 …"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from… [all …]
H A D	cache.json	42 …ts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exclud… 245 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 255 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 265 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 275 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 285 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 295 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 305 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 315 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 325 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	cache.json	16 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 27 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 36 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 45 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 213 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 217 "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 222 "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", 226 "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 700 "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", 710 "BriefDescription": "Counts all (cacheable) dat [all...]
H A D	other.json	363 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hav… 373 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 383 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 393 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 403 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 413 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 423 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 433 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 443 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 453 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… [all …]
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A D	cache.json	46 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 56 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 76 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 249 "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).", 431 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", 435 "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", 441 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 445 "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 451 "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", 455 "PublicDescription": "Counts the number of cacheable memor [all...]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	other.json	229 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 239 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 249 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 259 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 269 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 279 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 289 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 299 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 309 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 319 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand…
H A D	cache.json	24 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 35 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 53 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 62 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 291 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 295 "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 300 "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", 304 "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 762 "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", 772 "BriefDescription": "Counts all (cacheable) dat [all...]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	cache.json	24 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 35 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 53 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 62 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 291 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 295 "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 300 "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", 304 "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 743 "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", 753 "BriefDescription": "Counts all (cacheable) dat [all...]
H A D	other.json	199 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 209 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 219 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 229 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 239 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 249 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 259 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 269 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand…
/linux/arch/sparc/include/asm/
H A D	viking.h	`23 * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache 24 * 1 = Twalks are cacheable in E-cache 31 * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable 32 * 1 = Passthru physical accesses cacheable 34 * This indicates whether accesses are cacheable when no cachable bit`
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	cache.json	25 "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 320 "BriefDescription": "Core-originated cacheable demand requests missed L3", 324 "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", 329 "BriefDescription": "Core-originated cacheable demand requests that refer to L3", 333 "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", 592 "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", 606 "BriefDescription": "Cacheable and non-cacheable code read requests", 610 "PublicDescription": "This event counts both cacheable and non-cacheable cod [all...]
/linux/arch/riscv/include/asm/
H A D	pgtable-64.h	`116 * 00 - PMA Normal Cacheable, No change to implied PMA memory type 117 * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory 118 * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory 128 * bit[62] C - Cacheable 132 * 00110 - NC Weakly-ordered, Non-cacheable, Bufferable, Shareable, Non-trustable 133 * 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable 134 * 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable`
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	cache.json	24 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 35 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 44 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 53 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 300 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 304 "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 309 "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", 313 "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 702 "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", 712 "BriefDescription": "Counts all (cacheable) dat [all...]
/linux/arch/m68k/include/asm/
H A D	m53xxacr.h	`30 #define CACR_DCM_WT 0x00000000 /* Cacheable write-through / 31 #define CACR_DCM_CB 0x00000100 / Cacheable copy-back / 46 #define ACR_CM_WT 0x00000000 / Cacheable, write-through / 47 #define ACR_CM_CB 0x00000020 / Cacheable, copy-back */`
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/
H A D	cache.json	`35 …"PublicDescription": "L2 data cache refill. This event counts any cacheable transaction from L1 wh… 62 …"PublicDescription": "This event counts for any cacheable read transaction returning datafrom the … 67 …scription": "This event counts for any cacheable read transaction returning datafrom the SCU, or f…`
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	cache.json	25 "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 320 "BriefDescription": "Core-originated cacheable demand requests missed L3", 324 "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", 329 "BriefDescription": "Core-originated cacheable demand requests that refer to L3", 333 "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", 592 "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", 606 "BriefDescription": "Cacheable and non-cacheable code read requests", 610 "PublicDescription": "This event counts both cacheable and non-cacheable cod [all...]
/linux/arch/arm/mm/
H A D	proc-v7-2level.S	`19 /* PTWs cacheable, inner WB not shareable, outer WB not shareable / 23 / PTWs cacheable, inner WBWA shareable, outer WBWA not shareable / 116 IR = NMRR[2n+1:2n] - inner cacheable property 117 * OR = NMRR[2n+17:2n+16] - outer cacheable property`
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	cache.json	26 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 38 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 48 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 58 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 343 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", 347 "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", 353 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 357 "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 363 "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", 367 "PublicDescription": "Counts the number of cacheable memor [all...]
/linux/tools/perf/pmu-events/arch/x86/bonnell/
H A D	cache.json	`3 "BriefDescription": "L1 Data Cacheable reads and writes", 27 "BriefDescription": "L1 Cacheable Data Reads", 51 "BriefDescription": "L1 Cacheable Data Writes", 123 "BriefDescription": "L2 cacheable instruction fetch requests", 131 "BriefDescription": "L2 cacheable instruction fetch requests", 139 "BriefDescription": "L2 cacheable instruction fetch requests", 147 "BriefDescription": "L2 cacheable instruction fetch requests", 155 "BriefDescription": "L2 cacheable instruction fetch requests",`
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A D	memory.json	`30 "PublicDescription": "External memory request to non-cacheable memory", 33 "BriefDescription": "External memory request to non-cacheable memory"`
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	cache.json	16 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 27 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 36 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 45 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 231 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 235 "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 474 "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", 506 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 510 "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", 515 "BriefDescription": "Cycles when offcore outstanding cacheable Cor [all...]
/linux/arch/mips/include/asm/mach-ath79/
H A D	kernel-entry-init.h	`12 * 'Cacheable, noncoherent, write-through, no write allocate' 14 * 'Cacheable, noncoherent, write-back, write allocate'`

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