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Searched full:cacheable (Results 1 – 25 of 263) sorted by relevance

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/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A D	cache.json	5 …transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill resp… 140 …efDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable.", 152 …iption": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable.", 206 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 212 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 218 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 224 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 230 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 236 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… 242 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A D	cache.json	70 …efDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable.", 82 …iption": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable.", 136 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 142 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 148 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 154 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 160 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 166 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… 172 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… 178 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	cache.json	70 …efDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable.", 82 …iption": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable.", 136 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 142 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 148 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 154 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 160 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data … 166 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… 172 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… 178 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr… [all …]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	memory.json	71 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 81 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 91 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 101 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 111 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 121 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 301 …"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from… 311 …"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses… 321 …"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses… 331 …"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from… [all …]
H A D	cache.json	42 …ts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exclud… 245 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 255 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 265 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 275 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 285 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 295 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 305 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 315 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… 325 …"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that account… [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	cache.json	16 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 27 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 36 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema… 45 …hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable … 204 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… 208 …"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest La… 213 …"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetch… 217 …"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency c… 719 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 729 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… [all …]
H A D	other.json	363 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hav… 373 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 383 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 393 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 403 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 413 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 423 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 433 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 443 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 453 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… [all …]
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A D	cache.json	13 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… 17 …"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level C… 23 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… 27 …"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest La… 33 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on… 37 …"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Ca… 43 …"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetch… 47 …"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency c…
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	other.json	229 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 239 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 249 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 259 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 269 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 279 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 289 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 299 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 309 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 319 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand…
H A D	cache.json	24 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 35 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 53 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema… 62 …hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable … 291 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… 295 …"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest La… 300 …"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetch… 304 …"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency c… 788 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 798 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… [all …]
/linux/arch/sparc/include/asm/
H A D	viking.h	`23 * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache 24 * 1 = Twalks are cacheable in E-cache 31 * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable 32 * 1 = Passthru physical accesses cacheable 34 * This indicates whether accesses are cacheable when no cachable bit`
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	cache.json	24 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 35 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 53 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema… 62 …hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable … 291 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… 295 …"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest La… 300 …"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetch… 304 …"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency c… 767 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 777 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… [all …]
H A D	other.json	199 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 209 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 219 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 229 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 239 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 249 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 259 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 269 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand…
/linux/arch/riscv/include/asm/
H A D	pgtable-64.h	`116 * 00 - PMA Normal Cacheable, No change to implied PMA memory type 117 * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory 118 * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory 128 * bit[62] C - Cacheable 132 * 00110 - NC Weakly-ordered, Non-cacheable, Bufferable, Shareable, Non-trustable 133 * 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable 134 * 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable`
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	cache.json	25 …ardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable … 320 "BriefDescription": "Core-originated cacheable demand requests missed L3", 324 …"PublicDescription": "This event counts core-originated cacheable demand requests that miss the la… 329 "BriefDescription": "Core-originated cacheable demand requests that refer to L3", 333 …"PublicDescription": "This event counts core-originated cacheable demand requests that refer to th… 592 … counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 p… 606 "BriefDescription": "Cacheable and non-cacheable code read requests", 610 … "PublicDescription": "This event counts both cacheable and non-cacheable code read requests.", 642 …"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ),… 647 …"PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read… [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	cache.json	24 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 35 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 44 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema… 53 …hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable … 300 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… 304 …"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest La… 309 …"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetch… 313 …"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency c… 698 …"BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demand… 721 …"Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2… [all …]
/linux/arch/m68k/include/asm/
H A D	m53xxacr.h	`30 #define CACR_DCM_WT 0x00000000 /* Cacheable write-through / 31 #define CACR_DCM_CB 0x00000100 / Cacheable copy-back / 46 #define ACR_CM_WT 0x00000000 / Cacheable, write-through / 47 #define ACR_CM_CB 0x00000020 / Cacheable, copy-back */`
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/
H A D	cache.json	`35 …"PublicDescription": "L2 data cache refill. This event counts any cacheable transaction from L1 wh… 62 …"PublicDescription": "This event counts for any cacheable read transaction returning datafrom the … 67 …scription": "This event counts for any cacheable read transaction returning datafrom the SCU, or f…`
/linux/arch/arm/mm/
H A D	proc-v7-2level.S	`19 /* PTWs cacheable, inner WB not shareable, outer WB not shareable / 23 / PTWs cacheable, inner WBWA shareable, outer WBWA not shareable / 116 IR = NMRR[2n+1:2n] - inner cacheable property 117 * OR = NMRR[2n+17:2n+16] - outer cacheable property`
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	cache.json	25 …ardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable … 320 "BriefDescription": "Core-originated cacheable demand requests missed L3", 324 …"PublicDescription": "This event counts core-originated cacheable demand requests that miss the la… 329 "BriefDescription": "Core-originated cacheable demand requests that refer to L3", 333 …"PublicDescription": "This event counts core-originated cacheable demand requests that refer to th… 592 … counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 p… 606 "BriefDescription": "Cacheable and non-cacheable code read requests", 610 … "PublicDescription": "This event counts both cacheable and non-cacheable code read requests.", 642 …"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ),… 647 …"PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A D	memory.json	`30 "PublicDescription": "External memory request to non-cacheable memory", 33 "BriefDescription": "External memory request to non-cacheable memory"`
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	cache.json	26 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 38 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 48 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema… 58 …hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable … 343 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o… 347 …"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level C… 353 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… 357 …"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest La… 363 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on… 367 …"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Ca… [all …]
/linux/tools/perf/pmu-events/arch/x86/bonnell/
H A D	cache.json	`3 "BriefDescription": "L1 Data Cacheable reads and writes", 27 "BriefDescription": "L1 Cacheable Data Reads", 51 "BriefDescription": "L1 Cacheable Data Writes", 123 "BriefDescription": "L2 cacheable instruction fetch requests", 131 "BriefDescription": "L2 cacheable instruction fetch requests", 139 "BriefDescription": "L2 cacheable instruction fetch requests", 147 "BriefDescription": "L2 cacheable instruction fetch requests", 155 "BriefDescription": "L2 cacheable instruction fetch requests",`
/linux/arch/mips/include/asm/mach-ath79/
H A D	kernel-entry-init.h	`12 * 'Cacheable, noncoherent, write-through, no write allocate' 14 * 'Cacheable, noncoherent, write-back, write allocate'`
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	cache.json	16 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 27 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema… 36 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema… 45 …hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable … 222 …"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetche… 226 …"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest La… 485 …"Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2… 517 …"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ),… 521 …"PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactio… 526 …"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are pre… [all …]

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