Home
last modified time | relevance | path

Searched +full:cache +full:- +full:tauros2 (Results 1 – 12 of 12) sorted by relevance

/linux/Documentation/devicetree/bindings/cache/
H A Dmarvell,tauros2-cache.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cache/marvell,tauros2-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Tauros2 Cache
10 - Andrew Lunn <andrew@lunn.ch>
11 - Gregory Clement <gregory.clement@bootlin.com>
15 const: marvell,tauros2-cache
17 marvell,tauros2-cache-features:
19 Specify the features supported for the tauros2 cache. The features include:
[all …]
/linux/arch/arm/mm/
H A Dcache-tauros2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
8 * - PJ1 CPU Core Datasheet,
9 * Document ID MV-S104837-01, Rev 0.7, January 24 2008.
10 * - PJ4 CPU Core Datasheet,
11 * Document ID MV-S105190-00, Rev 0.7, March 14 2008.
20 #include <asm/hardware/cache-tauros2.h>
29 * When Tauros2 is used on a CPU that supports the v7 hierarchical
30 * cache operations, the cache handling code in proc-v7.S takes care
33 * So, we only need to register outer cache operations here if we're
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the linux arm-specific parts of the memory manager.
6 obj-y := extable.o fault.o init.o iomap.o
7 obj-y += dma-mapping$(MMUEXT).o
8 obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \
13 obj-y += nommu.o
14 obj-$(CONFIG_ARM_MPU) += pmsa-v7.o pmsa-v8.o
17 obj-$(CONFIG_ARM_PTDUMP_CORE) += dump.o
18 obj-$(CONFIG_ARM_PTDUMP_DEBUGFS) += ptdump_debugfs.o
19 obj-$(CONFIG_MODULES) += proc-syms.o
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
147 instruction sequences for cache and TLB operations. Curiously,
166 Branch Target Buffer, Unified TLB and cache line size 16.
182 ARM940T is a member of the ARM9TDMI family of general-
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dpxa910.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,pxa910.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bus";
25 interrupt-parent = <&intc>;
28 L2: l2-cache {
29 compatible = "marvell,tauros2-cache";
[all …]
H A Dmmp2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
9 #include <dt-bindings/clock/marvell,mmp2-audio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
[all …]
H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
[all …]
/linux/arch/arm/include/asm/hardware/
H A Dcache-tauros2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/include/asm/hardware/cache-tauros2.h
/linux/arch/arm/mach-mmp/
H A Dmmp2-dt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-mmp/mmp2-dt.c
12 #include <asm/hardware/cache-tauros2.h>
H A Dmmp-dt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-mmp/mmp-dt.c
12 #include <asm/hardware/cache-tauros2.h>
17 "mrvl,pxa168-aspenite",
22 "mrvl,pxa910-dkb",
/linux/arch/arm/mach-mvebu/
H A Ddove.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-mvebu/dove.c
12 #include <asm/hardware/cache-tauros2.h>
/linux/arch/arm/mach-dove/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-dove/common.c
8 #include <linux/clk-provider.h>
9 #include <linux/dma-mapping.h>
12 #include <linux/platform_data/dma-mv_xor.h>
13 #include <linux/platform_data/usb-ehci-orion.h>
16 #include <asm/hardware/cache-tauros2.h>
23 #include "bridge-regs.h"
27 /* These can go away once Dove uses the mvebu-mbus DT binding */
113 orion_clkdev_add(NULL, "orion-ehci.0", usb0); in dove_clk_init()
[all …]