| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 56 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
57 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
58 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
59 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
76 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
77 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
78 uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
79 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
80 uint32_t CLK1_CLK4_BYPASS_CNTL; //dtbclk bypass
92 uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
[all …]
|
| /linux/sound/soc/codecs/ |
| H A D | tlv320aic3x.c | 341 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
346 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
351 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
356 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
361 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
366 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
372 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
379 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
386 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
441 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volum
[all...] |
| H A D | isabelle.c | 414 SOC_SINGLE("ATX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
416 SOC_SINGLE("ATX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
418 SOC_SINGLE("ARX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
420 SOC_SINGLE("ARX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
422 SOC_SINGLE("ARX3 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
424 SOC_SINGLE("ARX4 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
426 SOC_SINGLE("ARX5 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
428 SOC_SINGLE("ARX6 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
430 SOC_SINGLE("VRX1 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
432 SOC_SINGLE("VRX2 Filter Bypass Switch", ISABELLE_AUDIO_HPF_CFG_REG,
[all …]
|
| /linux/include/linux/ |
| H A D | irqbypass.h | 3 * IRQ offload/bypass manager
19 * The IRQ bypass manager is a simple set of lists and callbacks that allows
21 * consumers (ex. virtualization hardware that allows IRQ bypass or offload)
35 * struct irq_bypass_producer - IRQ bypass producer definition
44 * The IRQ bypass producer structure represents an interrupt source for
45 * participation in possible host bypass, for instance an interrupt vector
61 * struct irq_bypass_consumer - IRQ bypass consumer definition
69 * The IRQ bypass consumer structure represents an interrupt sink for
70 * participation in possible host bypass, for instance a hypervisor may
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | frontend.json | 52 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
62 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
101 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
110 "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
138 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass th
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | frontend.json | 52 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
62 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
101 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
110 "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
138 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass th
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | frontend.json | 52 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
62 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
101 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
110 "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
138 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass th
[all...] |
| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | smsc,usb3503.yaml | 37 bypass-gpios:
40 GPIO for bypass.
41 Control signal to select between HUB MODE and BYPASS MODE.
57 Specifies initial mode. 1 for Hub mode, 2 for standby mode and 3 for bypass mode.
58 In bypass mode the downstream port 3 is connected to the upstream port with low
91 bypass-gpios: false
95 - bypass-gpios
138 bypass-gpios = <&gpx3 6 1>;
|
| /linux/include/trace/events/ |
| H A D | bcache.h | 124 TP_PROTO(struct bio *bio, bool hit, bool bypass),
125 TP_ARGS(bio, hit, bypass),
133 __field(bool, bypass )
142 __entry->bypass = bypass;
145 TP_printk("%d,%d %s %llu + %u hit %u bypass %u",
148 __entry->nr_sector, __entry->cache_hit, __entry->bypass)
153 bool writeback, bool bypass),
154 TP_ARGS(c, inode, bio, writeback, bypass),
163 __field(bool, bypass )
173 __entry->bypass = bypass;
[all …]
|
| /linux/drivers/regulator/ |
| H A D | anatop-regulator.c | 30 bool bypass; member
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
100 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) in anatop_regmap_core_get_voltage_sel()
113 WARN_ON(!anatop_reg->bypass); in anatop_regmap_get_bypass()
115 WARN_ON(anatop_reg->bypass); in anatop_regmap_get_bypass()
117 *enable = anatop_reg->bypass; in anatop_regmap_get_bypass()
126 if (enable == anatop_reg->bypass) in anatop_regmap_set_bypass()
130 anatop_reg->bypass = enable; in anatop_regmap_set_bypass()
270 sreg->bypass = true; in anatop_regulator_probe()
[all …]
|
| /linux/drivers/clk/sophgo/ |
| H A D | clk-cv18xx-ip.c | 311 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_round_rate()
338 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_recalc_rate()
349 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_set_rate()
359 if (cv1800_clk_checkbit(&div->div.common, &div->bypass)) in bypass_div_get_parent()
370 return cv1800_clk_clearbit(&div->div.common, &div->bypass); in bypass_div_set_parent()
372 return cv1800_clk_setbit(&div->div.common, &div->bypass); in bypass_div_set_parent()
522 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_round_rate()
549 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_recalc_rate()
560 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_set_rate()
570 if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass)) in bypass_mux_get_parent()
[all …]
|
| H A D | clk-cv18xx-ip.h | 32 struct cv1800_clk_regbit bypass; member
44 struct cv1800_clk_regbit bypass; member
52 struct cv1800_clk_regbit bypass; member
123 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
143 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
186 .bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
218 .bypass = CV1800_CLK_BIT(_bypass_reg, \
|
| /linux/virt/lib/ |
| H A D | irqbypass.c | 3 * IRQ offload/bypass manager
14 * bypass.
23 MODULE_DESCRIPTION("IRQ bypass manager utility module");
85 * irq_bypass_register_producer - register IRQ bypass producer
126 * irq_bypass_unregister_producer - unregister IRQ bypass producer
151 * irq_bypass_register_consumer - register IRQ bypass consumer
192 * irq_bypass_unregister_consumer - unregister IRQ bypass consumer
|
| /linux/drivers/clk/imx/ |
| H A D | clk-sscg-pll.c | 75 int bypass; member
146 temp_setup->bypass = PLL_BYPASS1; in clk_sscg_divq_lookup()
220 temp_setup->bypass = PLL_BYPASS_NONE; in clk_sscg_divf1_lookup()
280 setup->bypass = PLL_BYPASS2; in clk_sscg_pll_find_setup()
365 /* set bypass here too since the parent might be the same */ in clk_sscg_pll_set_rate()
368 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass); in clk_sscg_pll_set_rate()
405 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass); in clk_sscg_pll_set_parent()
416 int bypass) in __clk_sscg_pll_determine_rate() argument
427 switch (bypass) { in __clk_sscg_pll_determine_rate()
443 rate, bypass); in __clk_sscg_pll_determine_rate()
|
| /linux/drivers/clk/ti/ |
| H A D | clkt_dpll.c | 175 * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not
178 * Checks given DPLL enable bitfield to see whether the DPLL is in bypass
179 * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.
188 * Each set bit in the mask corresponds to a bypass value equal in _omap2_dpll_is_in_bypass()
217 /* Reparent the struct clk in case the dpll is in bypass */ in omap2_init_dpll_parent()
231 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
233 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
235 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
248 /* Return bypass rate if DPLL is bypassed */ in omap2_get_dpll_rate()
|
| H A D | dpll3xxx.c | 172 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
175 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
176 * bypass mode, the DPLL's rate is set equal to its parent clock's
179 * per the CDP code. If the DPLL entered bypass mode successfully,
180 * return 0; if the DPLL did not enter bypass in the time allotted, or
181 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
192 pr_debug("clock: configuring DPLL %s for low-power bypass\n", in _omap3_noncore_dpll_bypass()
509 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
512 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
514 * the same as the DPLL's parent clock, it will enter bypass;
[all …]
|
| /linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | dpll.txt | 5 (reference clock and bypass clock), with digital phase locked
36 and second entry bypass clock
55 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
79 ti,low-power-bypass;
|
| /linux/drivers/power/supply/ |
| H A D | bq25980_charger.c | 31 bool bypass; member
306 if (bq->state.bypass) in bq25980_set_input_curr_lim()
328 if (bq->state.bypass) { in bq25980_get_input_volt_lim()
350 if (bq->state.bypass) { in bq25980_set_input_volt_lim()
454 bq->state.bypass = en_bypass; in bq25980_set_bypass()
456 return bq->state.bypass; in bq25980_set_bypass()
604 state->bypass = chg_ctrl_2 & BQ25980_EN_BYPASS; in bq25980_get_state()
766 else if (state.bypass) in bq25980_get_charger_property()
768 else if (!state.bypass) in bq25980_get_charger_property()
828 old_state.bypass != new_state->bypass); in bq25980_state_changed()
[all …]
|
| /linux/drivers/base/regmap/ |
| H A D | regcache.c | 61 /* all registers are unreadable or volatile, so just bypass */ in regcache_hw_init()
77 /* Bypass the cache access till data read from HW */ in regcache_hw_init()
384 bool bypass; in regcache_sync() local
393 /* Remember the initial bypass state */ in regcache_sync()
394 bypass = map->cache_bypass; in regcache_sync()
424 /* Restore the bypass state */ in regcache_sync()
425 map->cache_bypass = bypass; in regcache_sync()
477 bool bypass; in regcache_sync_region() local
486 /* Remember the initial bypass state */ in regcache_sync_region()
487 bypass = map->cache_bypass; in regcache_sync_region()
[all …]
|
| /linux/Documentation/networking/ |
| H A D | nf_flowtable.rst | 21 transmitted to the output netdevice via neigh_xmit(), hence, packets bypass the
38 forwarding path including the Netfilter hooks and the flowtable fastpath bypass.
68 |__yes_________________fastpath bypass ____________________________|
84 Enabling the flowtable bypass is relatively easy, you only need to create a
109 forwarding bypass.
137 allows the flowtable to define a fastpath bypass between the bridge ports
143 fastpath bypass
|
| /linux/Documentation/devicetree/bindings/power/supply/ |
| H A D | bq25980.yaml | 54 ti,bypass-ovp-limit-microvolt:
61 ti,bypass-ocp-limit-microamp:
67 ti,bypass-enable:
69 description: Enables bypass mode at boot time
|
| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | frontend.json | 303 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
313 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
323 …the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During t…
333 …the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During t…
343 …(IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
353 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
363 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
372 …(IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
382 …truction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ.",
391 … Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This als…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | frontend.json | 303 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
313 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
323 …the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During t…
333 …the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During t…
343 …(IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
353 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
363 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
372 …(IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
382 …truction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ.",
391 … Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This als…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | frontend.json | 303 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
313 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
323 …the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During t…
333 …the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During t…
343 …(IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
353 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
363 … from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This ev…
372 …(IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
382 …truction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ.",
391 … Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This als…
[all …]
|
| /linux/arch/arm/mach-omap2/ |
| H A D | sram.h | 12 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
25 int bypass);
38 int bypass);
|