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/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-ocores.txt1 Device tree configuration for i2c-ocores
4 - compatible : "opencores,i2c-ocores"
6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC.
9 "sifive,fu740-c000-i2c", "sifive,i2c0"
11 FU740-C000 SoC.
12 Please refer to sifive-blocks-ip-versioning.txt for
14 - reg : bus address start and address range size of device
15 - clocks : handle to the controller clock; see the note below.
16 Mutually exclusive with opencores,ip-clock-frequency
[all …]
H A Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
[all …]
H A Di2c.txt7 Required properties (per bus)
8 -----------------------------
10 - #address-cells - should be <1>. Read more about addresses below.
11 - #size-cells - should be <0>.
12 - compatible - name of I2C bus controller
17 The cells properties above define that an address of children of an I2C bus
20 Optional properties (per bus)
21 -----------------------------
26 - clock-frequency
27 frequency of bus clock in Hz.
[all …]
H A Di2c-aspeed.txt4 - #address-cells : should be 1
5 - #size-cells : should be 0
6 - reg : address offset and range of bus
7 - compatible : should be "aspeed,ast2400-i2c-bus"
8 or "aspeed,ast2500-i2c-bus"
9 or "aspeed,ast2600-i2c-bus"
10 - clocks : root clock of bus, should reference the APB
12 - resets : phandle to reset controller with the reset number in
14 - interrupts : interrupt number
17 - bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not
[all …]
H A Daspeed,i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rayn Chen <rayn_chen@aspeedtech.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - aspeed,ast2400-i2c-bus
19 - aspeed,ast2500-i2c-bus
20 - aspeed,ast2600-i2c-bus
25 - description: address offset and range of bus
26 - description: address offset and range of bus buffer
[all …]
H A Di2c-qcom-cci.txt5 - compatible:
9 "qcom,msm8916-cci"
10 "qcom,msm8996-cci"
11 "qcom,sdm845-cci"
12 "qcom,sm8250-cci"
13 "qcom,sm8450-cci"
15 - reg
17 Value type: <prop-encoded-array>
21 - interrupts:
23 Value type: <prop-encoded-array>
[all …]
H A Di2c-pca-platform.txt4 parallel-bus microcontrollers/microprocessors and the serial I2C-bus
5 and allows the parallel bus system to communicate bi-directionally
6 with the I2C-bus.
10 - reg : Offset and length of the register set for the device
11 - compatible : one of "nxp,pca9564" or "nxp,pca9665"
14 - interrupts : the interrupt number
15 - reset-gpios : gpio specifier for gpio connected to RESET_N pin. As the line
17 - clock-frequency : I2C bus frequency.
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]
/freebsd/share/man/man4/
H A Diicbus.430 .Nd I2C bus system
41 system provides a uniform, modular and architecture-independent
45 I2C is an acronym for Inter Integrated Circuit bus.
46 The I2C bus was developed
49 easy way to connect a CPU to peripheral chips in a TV-set.
51 The BUS physically consists of 2 active wires and a ground connection.
56 Every component hooked up to the bus has its own unique address whether it
63 more BUS MASTERs.
65 The BUS MASTER is the chip issuing the commands on the BUS.
68 bus is considered the BUS MASTER.
[all …]
H A Dspigen.436 .Bd -ragged -offset indent
45 .Bd -literal -offset indent
51 driver provides direct access to a slave device on the SPI bus.
54 device is associated with a single chip-select
55 line on the bus, and all I/O performed through that instance is done
56 with that chip-select line asserted.
58 SPI data transfers are inherently bi-directional; there are no separate
75 .Bl -tag -width indent
83 .Bd -literal
91 The buffers for the transfer are a previously-mmap'd region.
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8186-evb.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 /dts-v1/;
10 chassis-type = "embedded";
11 compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
18 stdout-path = "serial0:921600n8";
30 clock-frequency = <400000>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&i2c0_pins>;
38 clock-frequency = <400000>;
39 i2c-scl-internal-delay-ns = <8000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-facebook-yosemite4.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/leds/leds-pca955x.h>
8 #include <dt-bindings/i2c/i2c.h>
12 compatible = "facebook,yosemite4-bmc", "aspeed,ast2600";
23 stdout-path = "serial4:57600n8";
31 iio-hwmon {
32 compatible = "iio-hwmon";
[all …]
H A Daspeed-g6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
6 #include <dt-bindings/clock/ast2600-clock.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
49 enable-method = "aspeed,ast2600-smp";
[all …]
H A Daspeed-g4.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
35 #address-cells = <1>;
36 #size-cells = <0>;
39 compatible = "arm,arm926ej-s";
51 compatible = "simple-bus";
52 #address-cells = <1>;
[all …]
H A Daspeed-g5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&vic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
40 compatible = "arm,arm1176jzf-s";
52 compatible = "simple-bus";
[all …]
H A Dibm-power10-dual.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #address-cells = <2>;
8 #size-cells = <0>;
10 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
14 #address-cells = <1>;
15 #size-cells = <1>;
16 chip-id = <0>;
24 compatible = "ibm,fsi-i2c-master";
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
H A Daspeed-bmc-delta-ahe50dc.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g4.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
9 compatible = "regulator-output"; \
10 vout-supply = <&efuse##n>; \
19 shunt-resistor-micro-ohms = <675>; \
22 regulator-name = __stringify(efuse##num##-reg); \
28 model = "Delta Power AHE-50DC";
29 compatible = "delta,ahe50dc-bmc", "aspeed,ast2400";
[all …]
/freebsd/sys/dts/arm/
H A Dannapurna-alpine.dts1 /*-
28 /dts-v1/;
32 #address-cells = <1>;
33 #size-cells = <1>;
40 #address-cells = <1>;
41 #size-cells = <0>;
45 compatible = "arm,cortex-a15";
47 d-cache-line-size = <64>; // 64 bytes
48 i-cache-line-size = <64>; // 64 bytes
49 d-cache-size = <0x8000>; // L1, 32K
[all …]
/freebsd/contrib/wpa/wpa_supplicant/examples/p2p/
H A Dp2p_group_add.py15 print(" %s -i <interface_name> [-p <persistent>] \ " \
17 print(" [-f <frequency>] [-o <group_object_path>] \ ")
18 print(" [-w <wpas_dbus_interface>]")
20 print(" -i = interface name")
21 print(" -p = persistent group = 0 (0=false, 1=true)")
22 print(" -f = frequency")
23 print(" -o = persistent group object path")
24 print(" -w = wpas dbus interface = fi.w1.wpa_supplicant1")
26 print(" %s -i wlan0" % sys.argv[0])
42 global bus
[all …]
/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Dexynos-bus.txt1 * Generic Exynos Bus frequency device
4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
5 for buses. Generally, each bus of Exynos SoC includes a source clock
6 and a power line, which are able to change the clock frequency
7 of the bus in runtime. To monitor the usage of each bus in runtime,
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
12 The each AXI bus has the owned source clock but, has not the only owned
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm2166x-common.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
11 #include <dt-bindings/clock/bcm21664.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 /* Hub bus */
20 hub: hub-bus@34000000 {
21 compatible = "simple-bus";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
[all...]
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dfsl,qe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 Basically, it is a bus of devices, that could act more or less
27 - const: fsl,qe
28 - const: simple-bus
40 bus-frequency:
42 description: the clock frequency for QUICC Engine.
44 fsl,qe-num-riscs:
[all …]
/freebsd/sys/dev/iicbus/
H A Diicbus.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 * Autoconfiguration and support routines for the Philips serial I2C bus
37 #include <sys/bus.h>
51 /* See comments below for why auto-scanning is a bad idea. */
60 device_set_desc(dev, "Philips I2C bus"); in iicbus_probe()
102 sc->dev = dev; in iicbus_attach_common()
103 mtx_init(&sc->lock, "iicbus", NULL, MTX_DEF); in iicbus_attach_common()
108 sc->strict = strict; in iicbus_attach_common()
110 sc->strict = 1; in iicbus_attach_common()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dcavium-mmc.txt10 - compatible : should be one of:
11 cavium,octeon-6130-mmc
12 cavium,octeon-7890-mmc
13 cavium,thunder-8190-mmc
14 cavium,thunder-8390-mmc
15 mmc-slot
16 - reg : mmc controller base registers
17 - clocks : phandle
20 - for cd, bus-width and additional generic mmc parameters
22 - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
17 which are able to change the clock frequency of the bus in runtime. To
[all …]

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