| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | ti,gpmc-child.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
[all …]
|
| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | renesas,nbpfaxi.txt | 1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
28 than using the maximum burst size allowed by the hardware's buffer size.
29 - max-burst-mem-write: limit burst size for memory writes
31 than using the maximum burst size allowed by the hardware's buffer size.
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
[all …]
|
| H A D | intel,ldma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
[all …]
|
| /linux/include/linux/platform_data/ |
| H A D | gpmc-omap.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
36 u32 cs_rd_off; /* Read deassertion time */
41 u32 adv_rd_off; /* Read deassertion time */
44 u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
59 u32 access; /* Start-cycle to first data valid delay */
60 u32 rd_cycle; /* Total read cycle time */
95 u32 t_rd_cycle; /* read cycle time */
96 u32 t_cez_r; /* read CS deassertion to high Z */
[all …]
|
| /linux/samples/pktgen/ |
| H A D | pktgen_sample03_burst_single_flow.sh | 2 # SPDX-License-Identifier: GPL-2.0
5 # - If correctly tuned[1], single CPU 10G wirespeed small pkts is possible[2]
7 # Using pktgen "burst" option (use -b $N)
8 # - To boost max performance
9 # - Avail since: kernel v3.18
10 # * commit 38b2cf2982dc73 ("net: pktgen: packet bursting via skb->xmit_more")
11 # - This avoids writing the HW tailptr on every driver xmit
12 # - The performance boost is impressive, see commit and blog [2]
19 # [1] http://netoptimizer.blogspot.dk/2014/06/pktgen-for-network-overload-testing.html
20 # [2] http://netoptimizer.blogspot.dk/2014/10/unlocked-10gbps-tx-wirespeed-smallest.html
[all …]
|
| H A D | pktgen_sample05_flow_per_thread.sh | 2 # SPDX-License-Identifier: GPL-2.0
4 # Script will generate one flow per thread (-t N)
5 # - Same destination IP
6 # - Fake source IPs for each flow (fixed based on thread number)
10 # separate-flow should not access shared variables/data. This script
24 if [ -z "$DEST_IP" ]; then
25 [ -z "$IP6" ] && DEST_IP="198.18.0.42" || DEST_IP="FD00::1"
27 [ -z "$DST_MAC" ] && DST_MAC="90:e2:ba:ff:ff:ff"
28 [ -z "$CLONE_SKB" ] && CLONE_SKB="0"
29 [ -z "$BURST" ] && BURST=32
[all …]
|
| H A D | pktgen_bench_xmit_mode_netif_receive.sh | 2 # SPDX-License-Identifier: GPL-2.0
5 # - developed for benchmarking ingress qdisc path
16 # ------------------------------------------------------------------
24 # (3) ingress on this dev, handle_ing() -> tc_classify()
42 if [ -z "$DEST_IP" ]; then
43 [ -z "$IP6" ] && DEST_IP="198.18.0.42" || DEST_IP="FD00::1"
45 [ -z "$DST_MAC" ] && DST_MAC="90:e2:ba:ff:ff:ff"
46 [ -z "$BURST" ] && BURST=1024
47 [ -z "$COUNT" ] && COUNT="10000000" # Zero means indefinitely
48 if [ -n "$DEST_IP" ]; then
[all …]
|
| H A D | pktgen_bench_xmit_mode_queue_xmit.sh | 2 # SPDX-License-Identifier: GPL-2.0
5 # - developed for benchmarking egress qdisc path, derived (more
21 if [ -z "$DEST_IP" ]; then
22 [ -z "$IP6" ] && DEST_IP="198.18.0.42" || DEST_IP="FD00::1"
24 [ -z "$DST_MAC" ] && DST_MAC="90:e2:ba:ff:ff:ff"
26 # Burst greater than 1 are invalid for queue_xmit mode
27 if [[ -n "$BURST" ]]; then
30 [ -z "$COUNT" ] && COUNT="10000000" # Zero means indefinitely
31 if [ -n "$DEST_IP" ]; then
33 read -r DST_MIN DST_MAX <<< $(parse_addr${IP6} $DEST_IP)
[all …]
|
| /linux/drivers/dma/qcom/ |
| H A D | hidma_mgmt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
17 #include <linux/dma-mapping.h>
45 "maximum write burst (default: ACPI/DT value)");
50 "maximum read burst (default: ACPI/DT value)");
60 "maximum number of read transactions (default: ACPI/DT value)");
67 if (!is_power_of_2(mgmtdev->max_write_request) || in hidma_mgmt_setup()
68 (mgmtdev->max_write_request < 128) || in hidma_mgmt_setup()
69 (mgmtdev->max_write_request > 1024)) { in hidma_mgmt_setup()
70 dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n", in hidma_mgmt_setup()
[all …]
|
| /linux/drivers/char/tpm/ |
| H A D | tpm_tis_i2c_cr50.c | 1 // SPDX-License-Identifier: GPL-2.0
10 * - Use an interrupt for transaction status instead of hardcoded delays.
11 * - Must use write+wait+read read protocol.
12 * - All 4 bytes of status register must be read/written at once.
13 * - Burst count max is 63 bytes, and burst count behaves slightly differently
15 * - When reading from FIFO the full burstcnt must be read instead of just
48 * struct tpm_i2c_cr50_priv_data - Driver private data.
63 * tpm_cr50_i2c_int_handler() - cr50 interrupt handler.
77 struct tpm_i2c_cr50_priv_data *priv = dev_get_drvdata(&chip->dev); in tpm_cr50_i2c_int_handler()
79 complete(&priv->tpm_ready); in tpm_cr50_i2c_int_handler()
[all …]
|
| /linux/drivers/dma/dw-edma/ |
| H A D | dw-edma-core.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
28 return &dchan->dev->device; in dchan2dev()
34 return &chan->vc.chan.dev->device; in chan2dev()
46 struct dw_edma_chip *chip = chan->dw->chip; in dw_edma_get_pci_address()
[all …]
|
| /linux/include/linux/iio/imu/ |
| H A D | adis.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
28 * struct adis_timeouts - ADIS chip variant timeouts
29 * @reset_ms - Wait time after rst pin goes inactive
30 * @sw_reset_ms - Wait time after sw reset command
31 * @self_test_ms - Wait time after self test command
40 * struct adis_data - ADIS chip variant specific data
41 * @read_delay: SPI delay for read operations in us
49 * @self_test_mask: Bitmask of supported self-test operations
51 * @self_test_no_autoclear: True if device's self-test needs clear of ctrl reg
[all …]
|
| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap2420-n8x0-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
53 #address-cells = <1>;
[all …]
|
| H A D | omap3-gta04a5one.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
[all …]
|
| /linux/drivers/media/pci/tw5864/ |
| H A D | tw5864-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
12 /* [15:0] The Version register for H264 core (Read Only) */
23 /* Enable bit for Host Burst Access */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
[all …]
|
| /linux/tools/testing/selftests/drivers/net/netdevsim/ |
| H A D | devlink_trap.sh | 2 # SPDX-License-Identifier: GPL-2.0
4 # This test is for checking devlink-trap functionality. It makes use of
40 if [ ! -d "$NETDEVSIM_PATH" ]; then
45 if [ -d "${NETDEVSIM_PATH}/devices/netdevsim${DEV_ADDR}" ]; then
54 if [ $((state & 1)) -ne 0 ]; then
65 test $(devlink_traps_num_get) -ne 0
80 # The action of non-drop traps cannot be changed.
137 check_fail $? "Did not get an error for non-existing trap"
139 log_test "Non-existing trap"
154 check_fail $? "Did not get an error for non-existing trap action"
[all …]
|
| /linux/arch/sparc/include/asm/ |
| H A D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
44 #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
46 #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
50 #define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
55 #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
56 #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
57 #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
58 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
62 #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
66 #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
[all …]
|
| /linux/include/linux/mtd/ |
| H A D | hyperbus.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
18 #define HYPERBUS_BT 0x20 /* Burst Type */
28 * struct hyperbus_device - struct representing HyperBus slave device
47 * struct hyperbus_ops - struct representing custom HyperBus operations
48 * @read16: read 16 bit of data from flash in a single burst. Used to read
50 * @write16: write 16 bit of data to flash in a single burst. Used to
69 * struct hyperbus_ctlr - struct representing HyperBus controller
82 * hyperbus_register_device - probe and register a HyperBus slave memory device
90 * hyperbus_unregister_device - deregister HyperBus slave memory device
|
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
[all …]
|
| H A D | snps,dwc-qos-ethernet.txt | 13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
|
| /linux/drivers/gpu/drm/nouveau/dispnv04/ |
| H A D | arb.c | 2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2007-2009 Stuart Bennett
38 int burst; member
63 pclk_freq = arb->pclk_khz; in nv04_calc_arb()
64 mclk_freq = arb->mclk_khz; in nv04_calc_arb()
65 nvclk_freq = arb->nvclk_khz; in nv04_calc_arb()
66 pagemiss = arb->mem_page_miss; in nv04_calc_arb()
67 cas = arb->mem_latency; in nv04_calc_arb()
68 bpp = arb->bpp; in nv04_calc_arb()
92 m1 = clwm + cbs - 512; in nv04_calc_arb()
[all …]
|
| /linux/drivers/misc/ |
| H A D | dw-xdata-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pci-epf.h>
20 #define DW_XDATA_DRIVER_NAME "dw-xdata-pcie"
75 return dw->rg_region.vaddr; in __dw_regs()
80 u32 burst; in dw_xdata_stop() local
82 mutex_lock(&dw->mutex); in dw_xdata_stop()
84 burst = readl(&(__dw_regs(dw)->burst_cnt)); in dw_xdata_stop()
86 if (burst & BURST_REPEAT) { in dw_xdata_stop()
87 burst &= ~(u32)BURST_REPEAT; in dw_xdata_stop()
88 writel(burst, &(__dw_regs(dw)->burst_cnt)); in dw_xdata_stop()
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/bonnell/ |
| H A D | other.json | 103 "BriefDescription": "Outstanding cacheable data read bus requests duration.",
111 "BriefDescription": "Outstanding cacheable data read bus requests duration.",
135 "BriefDescription": "Burst read bus transactions.",
143 "BriefDescription": "Burst read bus transactions.",
151 "BriefDescription": "Burst (full cache-line) bus transactions.",
159 "BriefDescription": "Burst (full cache-line) bus transactions.",
183 "BriefDescription": "Instruction-fetch bus transactions.",
191 "BriefDescription": "Instruction-fetch bus transactions.",
327 "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
|
| /linux/Documentation/scheduler/ |
| H A D | sched-bwc.rst | 7 The SCHED_RT case is covered in Documentation/scheduler/sched-rt-group.rst
14 microseconds of CPU time. That quota is assigned to per-cpu run queues in
22 is transferred to cpu-local "silos" on a demand basis. The amount transferred
25 Burst feature
26 -------------
30 Traditional (UP-EDF) bandwidth control is something like:
40 The burst feature observes that a workload doesn't always executes the full
62 The interferenece when using burst is valued by the possibilities for
66 https://lore.kernel.org/lkml/5371BD36-55AE-4F71-B9D7-B86DC32E3D2B@linux.alibaba.com/
69 ----------
[all …]
|
| /linux/drivers/net/ethernet/altera/ |
| H A D | altera_msgdmahw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
17 u32 burst_seq_num; /* bit 31:24 write burst
18 * bit 23:16 read burst
22 * bit 15:0 read stride
78 u32 status; /* Read/Clear */
79 u32 control; /* Read/Write */
80 u32 rw_fill_level; /* bit 31:16 - write fill level
81 * bit 15:0 - read fill level
84 u32 rw_seq_num; /* bit 31:16 - write sequence number
85 * bit 15:0 - read sequence number
|