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/linux/include/linux/usb/
H A Dr8a66597.h1 // SPDX-License-Identifier: GPL-2.0
124 #define XTAL 0xC000 /* b15-14: Crystal selection */
128 #define XCKE 0x2000 /* b13: External clock enable */
130 #define SCKE 0x0400 /* b10: USB clock enable */
133 #define HSE 0x0080 /* b7: Hi-speed enable */
135 #define DRPD 0x0020 /* b5: D+/- pull down control */
137 #define USBE 0x0001 /* b0: USB module operation enable */
140 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
141 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
143 #define IDMON 0x0004 /* b3: ID-pin monitor */
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/linux/drivers/media/platform/via/
H A Dvia-camera.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define VCR_IC_ACTBUF 0x0018 /* Active video buffer */
13 #define VCR_IC_INTEN 0x0100 /* End of active video int. enable */
14 #define VCR_IC_VBIINT 0x0200 /* End of VBI int enable */
15 #define VCR_IC_VBIBUF 0x0400 /* Current VBI buffer */
18 #define VCR_TSC_ENABLE 0x000001 /* Transport stream input enable */
20 #define VCR_TSC_METHOD 0x00000c /* DMA method (non-functional) */
22 #define VCR_TSC_CBMODE 0x080000 /* Change buffer by byte count */
28 #define VCR_CI_ENABLE 0x00000001 /* Capture enable */
31 #define VCR_CI_VIPEN 0x00000008 /* VIP enable */
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/linux/drivers/usb/renesas_usbhs/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-1.0+ */
100 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
101 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
102 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
103 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
107 #define SCKE (1 << 10) /* USB Module Clock Enable */
108 #define CNEN (1 << 8) /* Single-ended receiver operation Enable */
109 #define HSE (1 << 7) /* High-Speed Operation Enable */
111 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
113 #define USBE (1 << 0) /* USB Module Operation Enable */
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/linux/drivers/media/platform/st/sti/delta/
H A Ddelta-mjpeg-fw.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * @display_luma_p: address of the luma buffer
17 * @display_chroma_p: address of the chroma buffer
31 * @display_luma_p: address of the luma buffer
32 * @display_chroma_p: address of the chroma buffer
33 * @display_decimated_luma_p: address of the decimated luma buffer
34 * @display_decimated_chroma_p: address of the decimated chroma buffer
49 /* enable decimated (for display) reconstruction */
51 /* enable main (for display) reconstruction */
53 /* enable both main & decimated (for display) reconstruction */
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/linux/drivers/media/rc/
H A Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
18 #define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */
24 #define ENE_FW1_ENABLE 0x01 /* enable fw processing */
26 #define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/
27 #define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/
30 #define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
31 #define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
32 #define ENE_FW1_IRQ 0x80 /* enable interrupt */
36 #define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */
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/linux/drivers/gpu/drm/i915/
H A Di915_mitigations.c1 // SPDX-License-Identifier: MIT
41 return -ENOMEM; in mitigations_set()
44 bool enable = true; in mitigations_set() local
62 enable = !enable; in mitigations_set()
67 enable = !enable; in mitigations_set()
76 if (enable) in mitigations_set()
86 err = -EINVAL; in mitigations_set()
98 static int mitigations_get(char *buffer, const struct kernel_param *kp) in mitigations_get() argument
102 bool enable; in mitigations_get() local
105 return scnprintf(buffer, PAGE_SIZE, "%s\n", "off"); in mitigations_get()
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/linux/drivers/net/wan/
H A Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
24 #define DMER 0x09 /* DMA Master Enable */
32 #define IER0 0x14 /* Interrupt Enable 0 */
33 #define IER1 0x15 /* Interrupt Enable 1 */
34 #define IER2 0x16 /* Interrupt Enable 2 */
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL 0x00 /* TX/RX buffer L */
49 #define TRBH 0x01 /* TX/RX buffer H */
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/linux/drivers/pci/
H A Dvc.c1 // SPDX-License-Identifier: GPL-2.0
20 * pci_vc_save_restore_dwords - Save or restore a series of dwords
23 * @buf: buffer to save to or restore from
41 * pci_vc_load_arb_table - load and wait for VC arbitration table
64 * pci_vc_load_port_arb_table - Load and wait for VC port arbitration table
67 * @res: VC resource number, ie. VCn (0-7)
92 * pci_vc_enable - Enable virtual channel
95 * @res: VC res number, ie. VCn (0-7)
97 * A VC is enabled by setting the enable bit in matching resource control
99 * end of the link. To keep this simple we enable from the downstream device.
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/linux/kernel/trace/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 Enable generic return hooking feature. This is an internal
21 API, which will be used by other function-entry hooking
27 See Documentation/trace/ftrace-design.rst
32 See Documentation/trace/ftrace-design.rst
45 See Documentation/trace/ftrace-design.rst
95 See Documentation/trace/ftrace-desig
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dih_v6_1.c40 * ih_v6_1_init_register_offset - Initialize register offset for ih rings
52 if (adev->irq.ih.ring_size) { in ih_v6_1_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_1_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_1_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_1_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_1_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_1_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_1_init_register_offset()
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); in ih_v6_1_init_register_offset()
60 ih_regs->ih_rb_wptr_addr_l in ih_v6_1_init_register_offset()
129 ih_v6_1_toggle_ring_interrupts(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,bool enable) ih_v6_1_toggle_ring_interrupts() argument
170 ih_v6_1_toggle_interrupts(struct amdgpu_device * adev,bool enable) ih_v6_1_toggle_interrupts() argument
652 ih_v6_1_update_clockgating_state(struct amdgpu_device * adev,bool enable) ih_v6_1_update_clockgating_state() argument
687 ih_v6_1_update_ih_mem_power_gating(struct amdgpu_device * adev,bool enable) ih_v6_1_update_ih_mem_power_gating() argument
743 bool enable = (state == AMD_PG_STATE_GATE); ih_v6_1_set_powergating_state() local
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H A Diceland_ih.c38 * Starting with r6xx, interrupts are handled via a ring buffer.
45 * writes vectors to the ring buffer, it increments the
54 * iceland_ih_enable_interrupts - Enable the interrupt ring buffer
58 * Enable the interrupt ring buffer (VI).
69 adev->irq.ih.enabled = true; in iceland_ih_enable_interrupts()
73 * iceland_ih_disable_interrupts - Disable the interrupt ring buffer
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H A Dcz_ih.c38 * Starting with r6xx, interrupts are handled via a ring buffer.
45 * writes vectors to the ring buffer, it increments the
54 * cz_ih_enable_interrupts - Enable the interrupt ring buffer
58 * Enable the interrupt ring buffer (VI).
69 adev->irq.ih.enabled = true; in cz_ih_enable_interrupts()
73 * cz_ih_disable_interrupts - Disable the interrupt ring buffer
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/linux/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
41 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
54 /* Enable Length/Type error checking for incoming frames. When this option is
62 /* Enable the transmitter. Default: enabled (set) */
65 /* Enable the receiver. Default: enabled (set) */
92 #define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */
93 #define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
151 #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */
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H A Dxilinx_emaclite.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2007 - 2013 Xilinx, Inc.
31 #define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */
40 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
44 #define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */
60 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
62 /* Global Interrupt Enable Register (GIER) Bit Masks */
63 #define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */
68 #define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */
69 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit
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/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb_82598.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
10 #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
15 #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */
18 #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */
20 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet buffers enable */
21 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores (RSS) enable */
33 #define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */
35 #define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */
37 #define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */
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/linux/drivers/media/platform/ti/omap3isp/
H A Dispstat.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Statistics core
15 #include <linux/dma-mapping.h>
22 #define ISP_STAT_USES_DMAENGINE(stat) ((stat)->dma_ch != NULL)
36 * the next buffer to start to be written in the same point where the overflow
38 * go back to a valid state is having a valid buffer processing. Of course it
39 * requires at least a doubled buffer size to avoid an access to invalid memory
43 * configuration was created. It produces the minimum buffer size for each H3A
45 * will be enabled every time a SBL overflow occur. As the output buffer size
56 #define IS_H3A_AF(stat) ((stat) == &(stat)->isp->isp_af)
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/linux/arch/mips/include/asm/dec/
H A Dioasic_addrs.h53 #define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */
67 #define IO_REG_ISDN_T_DMA_BP 0x90 /* ISDN Transmit DMA Buffer Pointer */
69 #define IO_REG_ISDN_R_DMA_BP 0xb0 /* ISDN Receive DMA Buffer Pointer */
72 #define IO_REG_DATA_0 0xc0 /* System Data Buffer 0 */
73 #define IO_REG_DATA_1 0xd0 /* System Data Buffer 1 */
74 #define IO_REG_DATA_2 0xe0 /* System Data Buffer 2 */
75 #define IO_REG_DATA_3 0xf0 /* System Data Buffer 3 */
100 #define IO_REG_SCSI_SCR 0x1b0 /* SCSI Partial-Word DMA Control */
103 #define IO_REG_FCTR 0x1e0 /* Free-Running Counter */
115 #define IO_SSR_SCC0A_TX_DMA_EN (1<<31) /* SCC0A transmit DMA enable */
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/linux/drivers/net/wireless/nxp/nxpwifi/
H A D11h.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2011-2024 NXP
15 priv->state_11h.is_11h_enabled = true; in nxpwifi_init_11h_params()
16 priv->state_11h.is_11h_active = false; in nxpwifi_init_11h_params()
21 return priv->state_11h.is_11h_active; in nxpwifi_is_11h_active()
24 /* appends 11h info to a buffer while joining an infrastructure BSS */
26 nxpwifi_11h_process_infra_join(struct nxpwifi_private *priv, u8 **buffer, in nxpwifi_11h_process_infra_join() argument
36 if (!buffer || !(*buffer)) in nxpwifi_11h_process_infra_join()
39 radio_type = nxpwifi_band_to_radio_type((u8)bss_desc->bss_band); in nxpwifi_11h_process_infra_join()
40 sband = priv->wdev.wiphy->bands[radio_type]; in nxpwifi_11h_process_infra_join()
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/linux/arch/powerpc/
H A DKconfig.debug1 # SPDX-License-Identifier: GPL-2.0
4 bool "Don't build arch/powerpc code with -Werror"
7 arch/powerpc with the -Werror flag (which means warnings
10 Only enable this if you are hitting a build failure in the
47 emulated by the in-kernel emulator. Counters for the various classes
51 powerpc/emulated_instructions/do_warn in debugfs), rate-limited
56 bool "Run self-tests of the code-patching code"
60 bool "Enable use of jump label for cpu/mmu_has_feature()"
78 bool "Run self-tests of the feature-fixup code"
82 bool "Run self-tests of the MSI bitmap code"
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/linux/drivers/net/wireless/marvell/mwifiex/
H A D11h.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2011-2020 NXP
14 priv->state_11h.is_11h_enabled = true; in mwifiex_init_11h_params()
15 priv->state_11h.is_11h_active = false; in mwifiex_init_11h_params()
20 return priv->state_11h.is_11h_active; in mwifiex_is_11h_active()
22 /* This function appends 11h info to a buffer while joining an
26 mwifiex_11h_process_infra_join(struct mwifiex_private *priv, u8 **buffer, in mwifiex_11h_process_infra_join() argument
36 if (!buffer || !(*buffer)) in mwifiex_11h_process_infra_join()
39 radio_type = mwifiex_band_to_radio_type((u8) bss_desc->bss_band); in mwifiex_11h_process_infra_join()
40 sband = priv->wdev.wiphy->bands[radio_type]; in mwifiex_11h_process_infra_join()
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/linux/drivers/net/ethernet/intel/igc/
H A Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
22 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
23 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
24 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
25 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
26 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_FLX0 BIT(16) /* Flexible Filter 0 Enable */
29 #define IGC_WUFC_FLX1 BIT(17) /* Flexible Filter 1 Enable */
30 #define IGC_WUFC_FLX2 BIT(18) /* Flexible Filter 2 Enable */
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/linux/sound/firewire/dice/
H A Ddice-proc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dice_proc.c - a part of driver for Dice based devices
11 static int dice_proc_read_mem(struct snd_dice *dice, void *buffer, in dice_proc_read_mem() argument
17 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST, in dice_proc_read_mem()
19 buffer, 4 * quadlets, 0); in dice_proc_read_mem()
24 be32_to_cpus(&((u32 *)buffer)[i]); in dice_proc_read_mem()
45 for (i = 0; i < size - 2; ++i) { in dice_proc_fixup_string()
53 s[size - 1] = '\0'; in dice_proc_fixup_string()
57 struct snd_info_buffer *buffer) in dice_proc_read() argument
70 struct snd_dice *dice = entry->private_data; in dice_proc_read()
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/linux/drivers/mtd/nand/raw/
H A Dr852.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
31 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
44 /* card detection irq status & enable*/
46 #define R852_CARD_IRQ_ENABLE 0x07 /* IRQ enable */
52 #define R852_CARD_IRQ_GENABLE 0x80 /* general enable */
57 /* hardware enable */
71 /* physical DMA address - 32 bit value*/
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/linux/drivers/net/ethernet/actions/
H A Dowl-emac.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #define OWL_EMAC_DRVNAME "owl-emac"
49 #define OWL_EMAC_VAL_MAC_CSR5_TS_DATA 0x03 /* Transferring data HOST -> FIFO */
55 #define OWL_EMAC_VAL_MAC_CSR5_RS_DATA 0x07 /* Transferring data FIFO -> HOST */
59 #define OWL_EMAC_BIT_MAC_CSR5_GTE BIT(11) /* General-purpose timer expiration */
62 #define OWL_EMAC_BIT_MAC_CSR5_RU BIT(7) /* Receive buffer unavailable */
67 #define OWL_EMAC_BIT_MAC_CSR5_TU BIT(2) /* Transmit buffer unavailable */
93 /* Interrupt enable register */
95 #define OWL_EMAC_BIT_MAC_CSR7_NIE BIT(16) /* Normal interrupt summary enable */
96 #define OWL_EMAC_BIT_MAC_CSR7_AIE BIT(15) /* Abnormal interrupt summary enable */
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/linux/drivers/usb/gadget/udc/
H A Dm66592-udc.h1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2006-2007 Renesas Solutions Corp.
17 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
21 #define M66592_XCKE 0x2000 /* b13: External clock enable */
22 #define M66592_RCKE 0x1000 /* b12: Register clock enable */
24 #define M66592_SCKE 0x0400 /* b10: USB clock enable */
26 #define M66592_HSE 0x0080 /* b7: Hi-speed enable */
28 #define M66592_DMRPD 0x0020 /* b5: D- pull down control */
30 #define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */
31 #define M66592_PCUT 0x0002 /* b1: Low power sleep enable */
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