| /linux/Documentation/devicetree/bindings/fpga/ |
| H A D | fpga-region.yaml | 63 * FPGA Bridges gate bus signals between a host and FPGA.
64 * FPGA Bridges should be disabled while the FPGA is being programmed to
66 * FPGA bridges may be actual hardware or soft logic on an FPGA.
67 * During Full Reconfiguration, hardware bridges between the host and FPGA
72 buses, eliminating the need to show the hardware FPGA bridges in the
115 1. Disable appropriate FPGA bridges.
117 3. Enable the FPGA bridges.
122 will disable the bridges.
132 * FPGA Bridges
148 FPGA region will be the child of one of the hardware bridges (the bridge that
[all …]
|
| H A D | altr,freeze-bridge-controller.yaml | 10 The Altera Freeze Bridge Controller manages one or more freeze bridges.
11 The controller can freeze/disable the bridges which prevents signal
13 unfreeze/enable the bridges which allows traffic to pass through the bridge
|
| H A D | xlnx,pr-decoupler.yaml | 17 decouplers/fpga bridges. The controller can decouple/disable the bridges
19 can also couple / enable the bridges which allows traffic to pass through the
|
| /linux/drivers/gpu/drm/ |
| H A D | drm_bridge.c | 51 * either connected to it directly, or through a chain of bridges::
57 * Chaining multiple bridges to the output of a bridge, or the same bridge to
58 * the output of different bridges, is not supported.
74 * Bridges are responsible for linking themselves with the next bridge in the
78 * Once these links are created, the bridges can participate along with encoder
86 * bridges in the chain.
98 * Bridges also participate in implementing the &drm_connector at the end of
108 * The interaction between the bridges and other frameworks involved in
165 * DSI host interfaces are expected to be implemented as bridges rather than
399 * Add the given bridge to the global list of bridges, where they can be
[all …]
|
| /linux/drivers/fpga/ |
| H A D | fpga-bridge.c | 19 /* Lock for adding/removing bridges to linked lists*/
159 * fpga_bridges_enable - enable bridges in a list
160 * @bridge_list: list of FPGA bridges
182 * fpga_bridges_disable - disable bridges in a list
184 * @bridge_list: list of FPGA bridges
206 * fpga_bridges_put - put bridges
208 * @bridge_list: list of FPGA bridges
233 * @bridge_list: list of FPGA bridges
263 * @bridge_list: list of FPGA bridges
|
| H A D | fpga-region.c | 90 * bridges will be held if programming succeeds. This is intended to prevent
116 * In some cases, we already have a list of bridges in the in fpga_region_program_fpga()
117 * fpga region struct. Or we don't have any bridges. in fpga_region_program_fpga()
122 dev_err(dev, "failed to get fpga region bridges\n"); in fpga_region_program_fpga()
129 dev_err(dev, "failed to disable bridges\n"); in fpga_region_program_fpga()
141 dev_err(dev, "failed to enable region bridges\n"); in fpga_region_program_fpga()
253 * @get_bridges: optional function to get bridges to a list
|
| /linux/Documentation/driver-api/fpga/ |
| H A D | fpga-programming.rst | 12 the FPGA manager and bridges. It will:
16 * build a list of FPGA bridges if a method has been specified to do so
17 * disable the bridges
19 * re-enable the bridges
31 bridges to control during programming or it has a pointer to a function that
|
| H A D | intro.rst | 35 FPGA Bridges prevent spurious signals from going out of an FPGA or a
50 bridges as reconfigurable regions. A region may refer to the whole
|
| /linux/Documentation/driver-api/cxl/linux/example-configurations/ |
| H A D | hb-interleave.rst | 9 * CXL Root has Four (4) CXL Host Bridges
10 * Two CXL Host Bridges have a single CXL Memory Expander Attached
11 * The CXL root is configured to interleave across the two host bridges.
47 Host Bridges. The `Root` can be considered the singular upstream port attached
212 The next chunk shows the two CXL host bridges without attached endpoints.
|
| H A D | single-device.rst | 9 * CXL Root has Four (4) CXL Host Bridges
10 * One CXL Host Bridges has a single CXL Memory Expander Attached
47 Host Bridges. The `Root` can be considered the singular upstream port attached
145 The next chunk shows the three CXL host bridges without attached endpoints.
|
| H A D | multi-interleave.rst | 9 * CXL Root has Four (4) CXL Host Bridges
10 * Two CXL Host Bridges have a two CXL Memory Expanders Attached each.
11 * The CXL root is configured to interleave across the two host bridges.
48 Host Bridges. The `Root` can be considered the singular upstream port attached
288 The next chunk shows the two CXL host bridges without attached endpoints.
|
| H A D | intra-hb-interleave.rst | 9 * CXL Root has Four (4) CXL Host Bridges
10 * One (1) CXL Host Bridges has two CXL Memory Expanders Attached
47 Host Bridges. The `Root` can be considered the singular upstream port attached
183 The next chunk shows the three CXL host bridges without attached endpoints.
|
| /linux/Documentation/driver-api/cxl/linux/ |
| H A D | cxl-driver.rst | 27 Here is an example from a single-socket system with 4 host bridges. Two host
28 bridges have a single memory device attached, and the devices are interleaved
129 CXL `Host Bridges` in the fabric are probed during :code:`cxl_acpi_probe` at
186 In our example described above, there are four host bridges attached to the
187 root, and two of the host bridges have one endpoint attached.
263 of a root decoder are `Host Bridges`, which means interleave done at the root
271 <../platform/acpi/cedt>` and the UID field of CXL Host Bridges defined in
325 host bridges).
379 accesses over two host bridges. Each host bridge has a decoder which routes
504 attached to 4 host bridges, linux expects the following ways/granularity
|
| /linux/drivers/gpu/drm/tidss/ |
| H A D | tidss_kms.c | 33 * they enable the crtc before bridges' pre-enable, and disable the crtc in tidss_atomic_commit_tail()
34 * after bridges' post-disable. in tidss_atomic_commit_tail()
36 * Open code the functions here and first call the bridges' pre-enables, in tidss_atomic_commit_tail()
37 * then crtc enable, then bridges' post-enable (and vice versa for in tidss_atomic_commit_tail()
146 /* first find all the connected panels & bridges */ in tidss_dispc_modeset_init()
|
| /linux/Documentation/devicetree/bindings/ata/ |
| H A D | cortina,gemini-sata-bridge.yaml | 14 takes two Faraday Technology FTIDE010 PATA controllers and bridges
26 description: phandles to the reset lines for both SATA bridges
55 bridges.
|
| /linux/drivers/gpu/drm/bridge/ |
| H A D | megachips-stdpxxxx-ge-b850v3-fw.c | 11 * display bridge of the GE B850v3. There are two physical bridges on the video
13 * physical bridges are automatically configured by the input video signal, and
16 * STDP4028. The driver communicates with both bridges over i2c. The video
300 /* Only register after both bridges are probed */ in stdp4028_ge_b850v3_fw_probe()
347 /* Only register after both bridges are probed */ in stdp2690_ge_b850v3_fw_probe()
|
| /linux/arch/alpha/kernel/ |
| H A D | sys_eiger.c | 168 /* Find the number of backplane bridges. */ in eiger_swizzle()
173 case 0x00: bridge_count = 0; break; /* No bridges */ in eiger_swizzle()
182 /* Check for built-in bridges on hose 0. */ in eiger_swizzle()
192 /* Move up the chain of bridges. */ in eiger_swizzle()
|
| H A D | pci_impl.h | 15 * may also have PCI-PCI bridges present, and then we'd configure the
78 * A small note about bridges and interrupts. The DECchip 21050 (and
111 * pci_common_swizzle() handles multiple bridges. But there are a
|
| /linux/Documentation/driver-api/cxl/ |
| H A D | theory-of-operation.rst | 15 across host-bridges.
25 multiple Host Bridges and endpoints while another may opt for fault tolerance
39 module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
254 Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile
255 memory interleave that spans 2 Host Bridges, and a Volatile memory interleave
|
| /linux/drivers/fpga/tests/ |
| H A D | fpga-bridge-test.c | 106 /* Test the functions for getting and controlling a list of bridges */
132 /* Disable an then enable both bridges from the list */ in fpga_bridge_test_get_put_list()
145 /* Put and remove both bridges from the list */ in fpga_bridge_test_get_put_list()
|
| H A D | fpga-region-test.c | 115 * and control the bridges, and then the Manager for the actual programming.
154 * Region for getting and controlling bridges are tested (with a list of
155 * multiple bridges) in the Bridge suite.
|
| /linux/arch/arm/mach-omap2/ |
| H A D | omap4-common.c | 59 * The OMAP4 bus structure contains asynchronous bridges which can buffer
60 * data writes from the MPU. These asynchronous bridges can be found on
65 * therefore different asynchronous bridges.
95 * Async bridges can be found on paths between MPU to EMIF and MPU to L3
|
| /linux/drivers/pcmcia/ |
| H A D | o2micro.h | 114 * working. for some bridges it is at 0x94, for others at 0xD4. it's in o2micro_override()
115 * ok to write to both registers on all O2 bridges. in o2micro_override()
128 * older bridges have problems with both read prefetch and write in o2micro_override()
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-devices-pci-host-bridge | 6 controllers may also parent host bridges. The DDDD:BB format
10 for emulated host-bridges.
|
| /linux/Documentation/PCI/ |
| H A D | acpi-info.rst | 4 ACPI considerations for PCI host bridges
11 host bridges, so the ACPI namespace must describe each host bridge, the
44 PCI host bridges are PNP0A03 or PNP0A08 devices. Their _CRS should
93 bridges [8]. Since MCFG is a static table and can't be updated by hotplug,
|