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/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mtd/brcm,brcmnand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
27 -- Additional SoC-specific NAND controller properties --
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm63148.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "brcm,brahma-b15";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm6878.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm6855.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm63178.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm6756.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm47622.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
[all …]
H A Dbcm7445.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #address-cells = <2>;
6 #size-cells = <2>;
9 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "brcm,brahma-b15";
22 enable-method = "brcm,brahma-b15";
27 compatible = "brcm,brahma-b15";
[all …]
/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm6856.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm63146.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm6813.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm4912.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm63158.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
[all …]
H A Dbcm6858.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
14 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <0>;
21 compatible = "brcm,brahma-b53";
24 next-level-cache = <&L2_0>;
[all …]