182a58061SWilliam Zhang// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 282a58061SWilliam Zhang/* 382a58061SWilliam Zhang * Copyright 2022 Broadcom Ltd. 482a58061SWilliam Zhang */ 582a58061SWilliam Zhang 682a58061SWilliam Zhang#include <dt-bindings/interrupt-controller/irq.h> 782a58061SWilliam Zhang#include <dt-bindings/interrupt-controller/arm-gic.h> 882a58061SWilliam Zhang 982a58061SWilliam Zhang/ { 1082a58061SWilliam Zhang compatible = "brcm,bcm63146", "brcm,bcmbca"; 1182a58061SWilliam Zhang #address-cells = <2>; 1282a58061SWilliam Zhang #size-cells = <2>; 1382a58061SWilliam Zhang 1482a58061SWilliam Zhang interrupt-parent = <&gic>; 1582a58061SWilliam Zhang 1682a58061SWilliam Zhang cpus { 1782a58061SWilliam Zhang #address-cells = <2>; 1882a58061SWilliam Zhang #size-cells = <0>; 1982a58061SWilliam Zhang 2082a58061SWilliam Zhang B53_0: cpu@0 { 2182a58061SWilliam Zhang compatible = "brcm,brahma-b53"; 2282a58061SWilliam Zhang device_type = "cpu"; 2382a58061SWilliam Zhang reg = <0x0 0x0>; 2482a58061SWilliam Zhang next-level-cache = <&L2_0>; 2582a58061SWilliam Zhang enable-method = "psci"; 2682a58061SWilliam Zhang }; 2782a58061SWilliam Zhang 2882a58061SWilliam Zhang B53_1: cpu@1 { 2982a58061SWilliam Zhang compatible = "brcm,brahma-b53"; 3082a58061SWilliam Zhang device_type = "cpu"; 3182a58061SWilliam Zhang reg = <0x0 0x1>; 3282a58061SWilliam Zhang next-level-cache = <&L2_0>; 3382a58061SWilliam Zhang enable-method = "psci"; 3482a58061SWilliam Zhang }; 3582a58061SWilliam Zhang 3682a58061SWilliam Zhang L2_0: l2-cache0 { 3782a58061SWilliam Zhang compatible = "cache"; 38e567e58dSPierre Gondois cache-level = <2>; 390709e55eSKrzysztof Kozlowski cache-unified; 4082a58061SWilliam Zhang }; 4182a58061SWilliam Zhang }; 4282a58061SWilliam Zhang 4382a58061SWilliam Zhang timer { 4482a58061SWilliam Zhang compatible = "arm,armv8-timer"; 4582a58061SWilliam Zhang interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 4682a58061SWilliam Zhang <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 4782a58061SWilliam Zhang <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 4882a58061SWilliam Zhang <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 4982a58061SWilliam Zhang }; 5082a58061SWilliam Zhang 5182a58061SWilliam Zhang pmu: pmu { 5282a58061SWilliam Zhang compatible = "arm,cortex-a53-pmu"; 5382a58061SWilliam Zhang interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 5482a58061SWilliam Zhang <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5582a58061SWilliam Zhang interrupt-affinity = <&B53_0>, <&B53_1>; 5682a58061SWilliam Zhang }; 5782a58061SWilliam Zhang 5882a58061SWilliam Zhang clocks: clocks { 5982a58061SWilliam Zhang periph_clk: periph-clk { 6082a58061SWilliam Zhang compatible = "fixed-clock"; 6182a58061SWilliam Zhang #clock-cells = <0>; 6282a58061SWilliam Zhang clock-frequency = <200000000>; 6382a58061SWilliam Zhang }; 64f5d83b71SWilliam Zhang 6582a58061SWilliam Zhang uart_clk: uart-clk { 6682a58061SWilliam Zhang compatible = "fixed-factor-clock"; 6782a58061SWilliam Zhang #clock-cells = <0>; 6882a58061SWilliam Zhang clocks = <&periph_clk>; 6982a58061SWilliam Zhang clock-div = <4>; 7082a58061SWilliam Zhang clock-mult = <1>; 7182a58061SWilliam Zhang }; 72f5d83b71SWilliam Zhang 73f5d83b71SWilliam Zhang hsspi_pll: hsspi-pll { 74f5d83b71SWilliam Zhang compatible = "fixed-clock"; 75f5d83b71SWilliam Zhang #clock-cells = <0>; 76f5d83b71SWilliam Zhang clock-frequency = <200000000>; 77f5d83b71SWilliam Zhang }; 7882a58061SWilliam Zhang }; 7982a58061SWilliam Zhang 8082a58061SWilliam Zhang psci { 8182a58061SWilliam Zhang compatible = "arm,psci-0.2"; 8282a58061SWilliam Zhang method = "smc"; 8382a58061SWilliam Zhang }; 8482a58061SWilliam Zhang 8582a58061SWilliam Zhang axi@81000000 { 8682a58061SWilliam Zhang compatible = "simple-bus"; 8782a58061SWilliam Zhang #address-cells = <1>; 8882a58061SWilliam Zhang #size-cells = <1>; 8982a58061SWilliam Zhang ranges = <0x0 0x0 0x81000000 0x8000>; 9082a58061SWilliam Zhang 9182a58061SWilliam Zhang gic: interrupt-controller@1000 { 9282a58061SWilliam Zhang compatible = "arm,gic-400"; 9382a58061SWilliam Zhang #interrupt-cells = <3>; 9482a58061SWilliam Zhang interrupt-controller; 9582a58061SWilliam Zhang reg = <0x1000 0x1000>, 9682a58061SWilliam Zhang <0x2000 0x2000>, 9782a58061SWilliam Zhang <0x4000 0x2000>, 9882a58061SWilliam Zhang <0x6000 0x2000>; 9982a58061SWilliam Zhang interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 10082a58061SWilliam Zhang IRQ_TYPE_LEVEL_HIGH)>; 10182a58061SWilliam Zhang }; 10282a58061SWilliam Zhang }; 10382a58061SWilliam Zhang 10482a58061SWilliam Zhang bus@ff800000 { 10582a58061SWilliam Zhang compatible = "simple-bus"; 10682a58061SWilliam Zhang #address-cells = <1>; 10782a58061SWilliam Zhang #size-cells = <1>; 10882a58061SWilliam Zhang ranges = <0x0 0x0 0xff800000 0x800000>; 10982a58061SWilliam Zhang 110f5d83b71SWilliam Zhang hsspi: spi@1000 { 111f5d83b71SWilliam Zhang #address-cells = <1>; 112f5d83b71SWilliam Zhang #size-cells = <0>; 113f5d83b71SWilliam Zhang compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0"; 114f5d83b71SWilliam Zhang reg = <0x1000 0x600>; 115f5d83b71SWilliam Zhang interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 116f5d83b71SWilliam Zhang clocks = <&hsspi_pll &hsspi_pll>; 117f5d83b71SWilliam Zhang clock-names = "hsspi", "pll"; 118f5d83b71SWilliam Zhang num-cs = <8>; 119f5d83b71SWilliam Zhang status = "disabled"; 120f5d83b71SWilliam Zhang }; 121f5d83b71SWilliam Zhang 122*5319667cSWilliam Zhang nand_controller: nand-controller@1800 { 123*5319667cSWilliam Zhang #address-cells = <1>; 124*5319667cSWilliam Zhang #size-cells = <0>; 125*5319667cSWilliam Zhang compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; 126*5319667cSWilliam Zhang reg = <0x1800 0x600>, <0x2000 0x10>; 127*5319667cSWilliam Zhang reg-names = "nand", "nand-int-base"; 128*5319667cSWilliam Zhang status = "disabled"; 129*5319667cSWilliam Zhang 130*5319667cSWilliam Zhang nandcs: nand@0 { 131*5319667cSWilliam Zhang compatible = "brcm,nandcs"; 132*5319667cSWilliam Zhang reg = <0>; 133*5319667cSWilliam Zhang }; 134*5319667cSWilliam Zhang }; 135*5319667cSWilliam Zhang 13682a58061SWilliam Zhang uart0: serial@12000 { 13782a58061SWilliam Zhang compatible = "arm,pl011", "arm,primecell"; 13882a58061SWilliam Zhang reg = <0x12000 0x1000>; 13982a58061SWilliam Zhang interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 14082a58061SWilliam Zhang clocks = <&uart_clk>, <&uart_clk>; 14182a58061SWilliam Zhang clock-names = "uartclk", "apb_pclk"; 14282a58061SWilliam Zhang status = "disabled"; 14382a58061SWilliam Zhang }; 14482a58061SWilliam Zhang }; 14582a58061SWilliam Zhang}; 146