Home
last modified time | relevance | path

Searched +full:block +full:- +full:diagram (Results 1 – 25 of 86) sorted by relevance

1234

/linux/Documentation/gpu/amdgpu/display/
H A Ddcn-overview.rst8 generic diagram, and we have variations per ASIC.
10 .. kernel-figure:: dc_pipeline_overview.svg
12 Based on this diagram, we can pass through each block and briefly describe
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
24 multiple planes, using global or per-pixel alpha.
30 streams or divide capabilities. CRC values are generated in this block.
38 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
42 interrupts the controller to the SOC host interrupt unit. This block includes
43 the Display Micro-Controller Unit - version B (DMCUB), which is handled via
46 * **DCN Clock Generator Block (DCCG)**: It provides the clocks and resets
[all …]
/linux/Documentation/bpf/
H A Dmap_hash.rst1 .. SPDX-License-Identifier: GPL-2.0-only
3 .. Copyright (C) 2022-2023 Isovalent, Inc.
10 - ``BPF_MAP_TYPE_HASH`` was introduced in kernel version 3.19
11 - ``BPF_MAP_TYPE_PERCPU_HASH`` was introduced in version 4.6
12 - Both ``BPF_MAP_TYPE_LRU_HASH`` and ``BPF_MAP_TYPE_LRU_PERCPU_HASH``
20 to the max_entries limit that you specify. Hash maps use pre-allocation
22 used to disable pre-allocation when it is too memory expensive.
25 CPU. The per-cpu values are stored internally in an array.
40 **BPF_F_NO_COMMON_LRU** Per-CPU LRU, global map Per-CPU LRU, per-cpu map
41 **!BPF_F_NO_COMMON_LRU** Global LRU, global map Global LRU, per-cpu map
[all …]
/linux/Documentation/driver-api/nvdimm/
H A Dnvdimm.rst2 LIBNVDIMM: Non-Volatile Devices
5 libnvdimm - kernel / libndctl - userspace helper library
18 PMEM-REGIONs, Atomic Sectors, and DAX
40 LIBNVDIMM/LIBNDCTL: Block Translation Table "btt"
43 Summary LIBNDCTL Diagram
50 A system-physical-address range where writes are persistent. A
51 block device composed of PMEM is capable of DAX. A PMEM address range
55 DIMM Physical Address, is a DIMM-relative offset. With one DIMM in
56 the system there would be a 1:1 system-physical-address:DPA association.
59 system-physical-address.
[all …]
/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst1 .. SPDX-License-Identifier: GPL-2.0
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
20 In the below diagram, PCI NTB function configures the SoC with multiple
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
40 | | <-----------------------------------> | |
45 | +-------------+ +-------------+ |
[all …]
/linux/Documentation/admin-guide/media/
H A Dvimc.rst1 .. SPDX-License-Identifier: GPL-2.0
10 --------
12 The topology is hardcoded, although you could modify it in vimc-core and
17 .. kernel-figure:: vimc.dot
18 :alt: Diagram of the default media pipeline topology
29 If the configuration doesn't match, the stream will fail. The ``v4l-utils``
30 package is a bundle of user-space applications, that comes with ``media-ctl`` and
31 ``v4l2-ctl`` that can be used to configure the vimc configuration. This sequence
34 .. code-block:: bash
36 media-ctl -d platform:vimc -V '"Sensor A":0[fmt:SBGGR8_1X8/640x480]'
[all …]
H A Draspberrypi-pisp-be.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Raspberry Pi PiSP Back End Memory-to-Memory ISP (pisp-be)
10 The PiSP Back End is a memory-to-memory Image Signal Processor (ISP) which reads
19 tessellation and the computation of low-level configuration parameters is
24 an image sensor through a MIPI CSI-2 compatible capture interface, storing them
29 The pisp-be driver
32 The Raspberry Pi PiSP Back End (pisp-be) driver is located under
33 drivers/media/platform/raspberrypi/pisp-be. It uses the `V4L2 API` to register
38 The media topology registered by the `pisp-be` driver is represented below:
40 .. _pips-be-topology:
[all …]
H A Dimx.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
15 - Image DMA Controller (IDMAC)
16 - Camera Serial Interface (CSI)
17 - Image Converter (IC)
18 - Sensor Multi-FIFO Controller (SMFC)
19 - Image Rotator (IRT)
20 - Video De-Interlacing or Combining Block (VDIC)
25 image flip, 8x8 block transfer (see IRT description), pixel component
26 re-ordering (for example UYVY to YUYV) within the same colorspace, and
[all …]
/linux/Documentation/RCU/Design/Memory-Ordering/
H A DTree-RCU-Memory-Ordering.rst2 A Tour Through TREE_RCU's Grace-Period Memory Ordering
13 grace-period memory ordering guarantee is provided.
18 RCU grace periods provide extremely strong memory-ordering guarantees
19 for non-idle non-offline code.
22 period that are within RCU read-side critical sections.
25 of that grace period that are within RCU read-side critical sections.
27 Note well that RCU-sched read-side critical sections include any region
30 an extremely small region of preemption-disabled code, one can think of
37 a linked RCU-protected data structure, and phase two frees that element.
39 phase-one update (in the common case, removal) must not witness state
[all …]
/linux/Documentation/devicetree/bindings/hwmon/
H A Dbaikal,bt1-pvt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/baikal,bt1-pvt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 PVT Sensor
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 SoC provides an embedded process, voltage and temperature
17 which may cause the system instability and even damages. The IP-block
19 control wrapper, which provides a MMIO registers-based access to the
20 sensor core functionality (APB3-bus based) and exposes an additional
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,smi-larb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
19 - enum:
20 - mediatek,mt2701-smi-larb
21 - mediatek,mt2712-smi-larb
22 - mediatek,mt6779-smi-larb
[all …]
H A Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
31 - enum:
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
34 - mediatek,mt6779-smi-common
[all …]
/linux/Documentation/networking/pse-pd/
H A Dpse-pi.rst1 .. SPDX-License-Identifier: GPL-2.0
9 eight-pin modular jack, commonly known as the Ethernet RJ45 port. This
14 ---------------------------
19 - Section "33.2.3 PI pin assignments" covers the pin assignments for PoE
21 - Section "145.2.4 PSE PI" addresses the configuration for PoE systems that
25 -------------------------------
31 two pairs of wires, SPE operates on a simpler model due to its single-pair
33 assignments for power delivery, as described in the PSE PI for multi-pair
37 --------------------
47 ----------------------------
[all …]
/linux/include/uapi/linux/
H A Dethtool.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
26 * have the same layout for 32-bit and 64-bit userland.
38 * struct ethtool_cmd - DEPRECATED, link control and status
43 * interface supports autonegotiation or auto-detection.
44 * Read-only.
48 * auto-detection.
56 * @autoneg: Enable/disable autonegotiation and auto-detection;
60 * Read-only.
62 * obsoleted by &struct ethtool_coalesce. Read-only; deprecated.
64 * obsoleted by &struct ethtool_coalesce. Read-only; deprecated.
[all …]
/linux/Documentation/RCU/Design/Expedited-Grace-Periods/
H A DExpedited-Grace-Periods.rst13 There are two flavors of RCU (RCU-preempt and RCU-sched), with an earlier
14 third RCU-bh flavor having been implemented in terms of the other two.
38 RCU-preempt Expedited Grace Periods
41 ``CONFIG_PREEMPTION=y`` kernels implement RCU-preempt.
42 The overall flow of the handling of a given CPU by an RCU-preempt
43 expedited grace period is shown in the following diagram:
45 .. kernel-figure:: ExpRCUFlow.svg
59 can check to see if the CPU is currently running in an RCU read-side
63 invocation will provide the needed quiescent-state report.
64 This flag-setting avoids the previous forced preemption of all
[all …]
/linux/fs/xfs/libxfs/
H A Dxfs_attr.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2000,2002-2003,2005 Silicon Graphics, Inc.
18 * The internal links in the Btree are logical block offsets into the file.
32 * Kernel-internal version of the attrlist cursor.
36 __u32 blkno; /* block containing entry (suggestion) */
37 __u32 offset; /* offset in list of equal-hashvals */
38 __u16 pad1; /* padding to match user-level */
39 __u8 pad2; /* padding to match user-level */
61 * Abort attribute list iteration if non-zero. Can be used to pass
85 * Below is a state machine diagram for attr remove operations. The XFS_DAS_*
[all …]
/linux/Documentation/devicetree/bindings/iommu/
H A Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
18 About the M4U Hardware Block Diagram, please check below:
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Drealtek,rtd1315e-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/realtek,rtd1315e-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - TY Chang <tychang@realtek.com>
14 The Realtek DHC RTD1315E is a high-definition media processor SoC. The
20 const: realtek,rtd1315e-pinctrl
26 '-pins$':
29 - $ref: pincfg-node.yaml#
30 - $ref: pinmux-node.yaml#
[all …]
H A Drealtek,rtd1619b-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/realtek,rtd1619b-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - TY Chang <tychang@realtek.com>
14 The Realtek DHC RTD1619B is a high-definition media processor SoC. The
20 const: realtek,rtd1619b-pinctrl
26 '-pins$':
29 - $ref: pincfg-node.yaml#
30 - $ref: pinmux-node.yaml#
[all …]
H A Drealtek,rtd1319d-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/realtek,rtd1319d-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - TY Chang <tychang@realtek.com>
14 The Realtek DHC RTD1319D is a high-definition media processor SoC. The
20 const: realtek,rtd1319d-pinctrl
26 '-pins$':
29 - $ref: pincfg-node.yaml#
30 - $ref: pinmux-node.yaml#
[all …]
/linux/Documentation/driver-api/
H A Dvfio-mediated-device.rst1 .. SPDX-License-Identifier: GPL-2.0-only
17 The number of use cases for virtualizing DMA devices that do not have built-in
25 an IOMMU/device-agnostic framework for exposing direct device access to user
26 space in a secure, IOMMU-protected environment. This framework is used for
44 The following high-level block diagram shows the main components and interfaces
45 in the VFIO mediated driver framework. The diagram shows NVIDIA, Intel, and IBM
48 +---------------+
50 | +-----------+ | mdev_register_driver() +--------------+
51 | | | +<------------------------+ |
53 | | bus | +------------------------>+ vfio_mdev.ko |<-> VFIO user
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,vcodec-subdev-decoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yunfei Dong <yunfei.dong@mediatek.com>
18 About the Decoder Hardware Block Diagram, please check below:
20 +------------------------------------------------+-------------------------------------+
22 | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
24 +------------||-------------||-------------------+---------------------||--------------+
26 -------------||-------------||-------------------|---------------------||---------------
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
[all …]
/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,flexgen.txt5 - a clock cross bar (represented by a mux element)
6 - a pre and final dividers (represented by a divider and gate elements)
12 Clockgen block diagram
13 -------------------------------------------------------------------
15 | --------------------------------------------- |
16 | | ------- -------- -------- | |
18 ---|-----------------|-->| | | | | | | |
20 | | ------- | | | |Pre | |Final | | |
22 | |->| | | | | | x32 | | x32 | | |
23 | | | odf_0|----|-->| | | | | | | |
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <jianjun.wang@mediatek.com>
17 block diagram is as follows:
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
[all …]
/linux/Documentation/sound/cards/
H A Dmaya44.rst8 keep here as reference -- tiwai
22 … programming information, so I (Rainer Zimmermann) had to find out some card-specific information …
24 This is the first testing version of the Maya44 driver released to the alsa-devel mailing list (Feb…
29 - playback and capture at all sampling rates
30 - input/output level
31 - crossmixing
32 - line/mic switch
33 - phantom power switch
34 - analogue monitor a.k.a bypass
39 - Channel 3+4 analogue - S/PDIF input switching
[all …]

1234