| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap24xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
31 #clock-cells = <0>;
[all …]
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| H A D | omap2430-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
31 #clock-cells = <0>;
32 compatible = "ti,composite-clock";
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| H A D | omap2420-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
32 #clock-cells = <0>;
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| H A D | omap44xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
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| H A D | omap54xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
25 #clock-cells = <0>;
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| H A D | am43xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_reg_utils.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
65 /** get field out of 32 bit register */
66 #define AL_REG_FIELD_GET(reg, mask, shift) (((reg) & (mask)) >> (shift)) argument
68 /** set field of 32 bit register */
69 #define AL_REG_FIELD_SET(reg, mask, shift, val) \ argument
72 ((((unsigned)(val)) << (shift)) & (mask)))
74 /** set field of 64 bit register */
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ti/ |
| H A D | gate.txt | 4 quite much similar to the basic gate-clock [2], however,
7 will be controlled instead and the corresponding hw-ops for
10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
11 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
15 - compatible : shall be one of:
16 "ti,gate-clock" - basic gate clock
17 "ti,wait-gate-clock" - gate clock which waits until clock is active before
19 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
20 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
21 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
[all …]
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| H A D | divider.txt | 4 register-mapped adjustable clock rate divider that does not gate and has
15 ti,index-starts-at-one - valid divisor values start at 1, not the default
22 ti,index-power-of-two - valid divisor values are powers of two. E.g:
39 Any zero value in this array means the corresponding bit-value is invalid
44 the number of bits to shift that mask, if necessary. If the shift value
45 is missing it is the same as supplying a zero shift.
50 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
54 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
55 - #clock-cells : from common clock binding; shall be set to 0.
56 - clocks : link to phandle of parent clock
[all …]
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| H A D | mux.txt | 4 register-mapped multiplexer with multiple input clock signals or
22 "index-starts-at-one" modified the scheme as follows:
30 the number of bits to shift the control field in the register can be
31 supplied. If the shift value is missing it is the same as supplying
32 a zero shift.
34 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
37 - compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
38 - #clock-cells : from common clock binding; shall be set to 0.
39 - clocks : link phandles of parent clocks
40 - reg : register offset for register controlling adjustable mux
[all …]
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| H A D | autoidle.txt | 5 and a configuration bit setting. Autoidle clock is never an individual
7 or fixed-factor.
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - reg : offset for the register controlling the autoidle
13 - ti,autoidle-shift : bit shift of the autoidle enable bit
14 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
18 #clock-cells = <0>;
19 compatible = "ti,divider-clock";
21 ti,max-div = <31>;
22 ti,autoidle-shift = <8>;
[all …]
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| H A D | interface.txt | 4 quite much similar to the basic gate-clock [2], however,
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
13 - compatible : shall be one of:
14 "ti,omap3-interface-clock" - basic OMAP3 interface clock
15 "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
17 "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
19 "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
20 "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
21 "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | anatop-regulator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: regulator.yaml#
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
25 anatop-vol-bit-shift:
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | ScaledNumber.h | 1 //===- llvm/Support/ScaledNumber.h - Support for scaled numbers -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // numbers -- in particular, pairs of integers where one represents digits and
13 // certain cost metrics that need simple, integer-like semantics that are easy
16 // These might remind you of soft-floats. If you want one of those, you're in
19 //===----------------------------------------------------------------------===//
39 const int32_t MinScale = -16382;
59 return std::make_pair(DigitsT(1) << (getWidth<DigitsT>() - 1), Scale + 1); in getRounded()
63 /// Convenience helper for 32-bit rounding.
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| /freebsd/crypto/openssl/doc/man3/ |
| H A D | EVP_des_cbc.pod | 27 - EVP DES cipher
54 DES in CBC, ECB, CFB with 64-bit shift, CFB with 1-bit shift, CFB with 8-bit
55 shift and OFB modes.
68 Two key triple DES in ECB, CBC, CFB with 64-bit shift and OFB modes.
79 Three-key triple DES in ECB, CBC, CFB with 64-bit shift, CFB with 1-bit shift,
80 CFB with 8-bit shift and OFB modes.
84 Triple-DES key wrap according to RFC 3217 Section 3.
92 L<EVP_CIPHER_fetch(3)> with L<EVP_CIPHER-DES(7)> instead.
109 Copyright 2017-2023 The OpenSSL Project Authors. All Rights Reserved.
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface -------
[all...] |
| H A D | AVRShiftExpand.cpp | 1 //===- AVRShift.cpp - Shift Expansion Pass --------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// Expand non-8-bit and non-16-bit shift instructions (shl, lshr, ashr) to
11 /// inline loops, just like avr-gcc. This must be done in IR because otherwise
12 /// the type legalizer will turn 32-bit shifts into (non-existing) library calls
15 //===----------------------------------------------------------------------===//
33 StringRef getPassName() const override { return "AVR Shift Expansion"; } in getPassName()
43 INITIALIZE_PASS(AVRShiftExpand, "avr-shift-expand", "AVR Shift Expansion",
53 // Only expand shift instructions (shl, lshr, ashr). in runOnFunction()
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | keystone-pll.txt | 9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
23 #clock-cells = <0>;
24 compatible = "ti,keystone,main-pll-clock";
[all …]
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| /freebsd/sys/contrib/dev/rtw88/ |
| H A D | hci.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
40 return rtwdev->hci.ops->tx_write(rtwdev, pkt_info, skb); in rtw_hci_tx_write()
45 return rtwdev->hci.ops->tx_kick_off(rtwdev); in rtw_hci_tx_kick_off()
50 return rtwdev->hci.ops->setup(rtwdev); in rtw_hci_setup()
55 return rtwdev->hci.ops->start(rtwdev); in rtw_hci_start()
60 rtwdev->hci.ops->stop(rtwdev); in rtw_hci_stop()
65 rtwdev->hci.ops->deep_ps(rtwdev, enter); in rtw_hci_deep_ps()
70 rtwdev->hci.ops->link_ps(rtwdev, enter); in rtw_hci_link_ps()
75 rtwdev->hci.ops->interface_cfg(rtwdev); in rtw_hci_interface_cfg()
[all …]
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| /freebsd/sys/compat/linuxkpi/common/include/linux/ |
| H A D | bitops.h | 1 /*-
5 * Copyright (c) 2013-2017 Mellanox Technologies, Ltd.
38 #define BIT(nr) (1UL << (nr)) macro
44 #define BITMAP_LAST_WORD_MASK(n) (~0UL >> (BITS_PER_LONG - (n)))
46 #define BIT_MASK(nr) (1UL << ((nr) & (BITS_PER_LONG - 1)))
48 #define GENMASK(h, l) (((~0UL) >> (BITS_PER_LONG - (h) - 1)) & ((~0UL) << (l)))
49 #define GENMASK_ULL(h, l) (((~0ULL) >> (BITS_PER_LONG_LONG - (h) - 1)) & ((~0ULL) << (l)))
68 return (ffs(mask) - 1); in __ffs()
74 return (fls(mask) - 1); in __fls()
80 return (ffsl(mask) - 1); in __ffsl()
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| /freebsd/secure/lib/libcrypto/man/man3/ |
| H A D | EVP_des_cbc.3 | 1 .\" -*- mode: troff; coding: utf-8 -*-
58 .TH EVP_DES_CBC 3ossl 2025-09-30 3.5.4 OpenSSL
86 \&\- EVP DES cipher
102 DES in CBC, ECB, CFB with 64\-bit shift, CFB with 1\-bit shift, CFB with 8\-bit
103 shift and OFB modes.
110 Two key triple DES in ECB, CBC, CFB with 64\-bit shift and OFB modes.
113 Three-key triple DES in ECB, CBC, CFB with 64\-bit shift, CFB with 1\-bit shift,
114 CFB with 8\-bit shift and OFB modes.
117 Triple-DES key wrap according to RFC 3217 Section 3.
122 \&\fBEVP_CIPHER_fetch\fR\|(3) with \fBEVP_CIPHER\-DES\fR\|(7) instead.
[all …]
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| /freebsd/contrib/llvm-project/libcxx/src/include/ryu/ |
| H A D | d2s_intrinsics.h | 1 //===----------
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandImm.cpp | 1 //===- AArch64ExpandImm.h - AArch64 Immediate Expansion -------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
20 /// Helper function which extracts the specified 16-bit chunk from a
21 /// 64-bit value.
28 /// Check whether the given 16-bit chunk replicated to full 64-bit width
36 /// Check for identical 16-bit chunks within the constant and if so
38 /// 16-bit chunks will be materialized with MOVK instructions.
152 const int NotSet = -1; in trySequenceOfOnes()
[all …]
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| /freebsd/sys/sys/ |
| H A D | _atomic_subword.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 * simply do not do sub-word atomic operations. These are not ideal as they
51 (uint32_t *)((__uintptr_t)(p) - ((__uintptr_t)(p) % 4))
55 ((3 - ((__uintptr_t)(p) % 4)) * NBBY)
58 ((2 - ((__uintptr_t)(p) % 4)) * NBBY)
85 * operation fails due to the other half-word resident in that word, in _atomic_cmpset_masked_word()
86 * rather than the half-word we're trying to operate on. Ideally we in _atomic_cmpset_masked_word()
121 int shift; in atomic_cmpset_8() local
123 shift = _ATOMIC_BYTE_SHIFT(addr); in atomic_cmpset_8()
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| /freebsd/share/man/man4/ |
| H A D | keyboard.4 | 23 then enter a decimal number from 0-255 via the numerical keypad, then
31 pressing the scroll-lock key.
40 .Bl -tag -width "Modifier Key" -compact
55 of the key is transmitted as an 8 bit char with bit 7 as 0 when a key is
56 pressed, and the number with bit 7 as 1 when released.
64 .Bd -literal -offset indent
80 on the shift, control, and alt state.
83 .Bd -literal
86 code base shift cntrl shift alt shift cntrl shift
88 ---- ------------------------------------------------------
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