1 //===- AArch64ExpandImm.h - AArch64 Immediate Expansion -------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
20 /// Helper function which extracts the specified 16-bit chunk from a
21 /// 64-bit value.
28 /// Check whether the given 16-bit chunk replicated to full 64-bit width
36 /// Check for identical 16-bit chunks within the constant and if so
38 /// 16-bit chunks will be materialized with MOVK instructions.
152   const int NotSet = -1;  in trySequenceOfOnes()
160     // Sign extend the 16-bit chunk to 64-bit.  in trySequenceOfOnes()
220   // Create the ORR-immediate instruction.  in trySequenceOfOnes()
249     UnshiftedOnes = (1ULL << NumOnes) - 1;  in GetRunOfOnesStartingAt()
259     uint64_t Rotation = 1ULL << (6 - i);  in MaximallyReplicateSubImmediate()
274   // Find the first set bit.  in maximalLogicalImmWithin()
310   // Make sure to un-rotate the immediates.  in decomposeIntoOrrOfLogicalImmediates()
321   uint64_t Imm1 = MaybeDecomposition->first;  in tryOrrOfLogicalImmediates()
322   uint64_t Imm2 = MaybeDecomposition->second;  in tryOrrOfLogicalImmediates()
329     // Create the ORR-immediate instructions.  in tryOrrOfLogicalImmediates()
347   uint64_t Imm1 = MaybeDecomposition->first;  in tryAndOfLogicalImmediates()
348   uint64_t Imm2 = MaybeDecomposition->second;  in tryAndOfLogicalImmediates()
365 // Check whether the constant can be represented by exclusive-or of two 64-bit
370 // 16-bit values, to be encoded without needing four instructions. It can also
381     uint64_t Mask = (1ULL << BigSize) - 1;  in tryEorOfLogicalImmediates()
389   uint64_t BigMask = ((uint64_t)-1LL) >> (64 - BigSize);  in tryEorOfLogicalImmediates()
391   // Find the last bit of each run of ones, circularly. For runs which wrap  in tryEorOfLogicalImmediates()
392   // around from bit 0 to bit 63, this is the bit before the most-significant  in tryEorOfLogicalImmediates()
393   // zero, otherwise it is the least-significant bit in the run of ones.  in tryEorOfLogicalImmediates()
397   // counting the number of runs of one-bits within the BigSize-bit value. Both  in tryEorOfLogicalImmediates()
399   // power-of-two count that can be represented by a logical immediate, or it  in tryEorOfLogicalImmediates()
404       -1, -1, 0,  1,  2,  2,  -1, 3,  3,  3,  -1, -1, -1, -1, -1, 4,  in tryEorOfLogicalImmediates()
405       4,  4,  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5,  in tryEorOfLogicalImmediates()
410   // Early-exit if the big chunk couldn't be a power-of-two number of runs  in tryEorOfLogicalImmediates()
412   if (BigToSmallShift == -1)  in tryEorOfLogicalImmediates()
417   // 64-bit values with a bit set every (1 << index) bits.  in tryEorOfLogicalImmediates()
425   // 0xffffffffffffffff / ((1 << SmallSize) - 1), and can be thought of as  in tryEorOfLogicalImmediates()
426   // dividing the 64-bit value into fields of width SmallSize, and placing a  in tryEorOfLogicalImmediates()
427   // one in the least significant bit of each field.  in tryEorOfLogicalImmediates()
444         rotl<uint64_t>((SmallOnes << RunLength) - SmallOnes, Rotation);  in tryEorOfLogicalImmediates()
472   // more MOVK instructions to insert additional 16-bit portions into the  in expandMOVImmSimple()
485     Imm &= (1LL << 32) - 1;  in expandMOVImmSimple()
490   unsigned Shift = 0;     // LSL amount for high bits with MOVZ/MOVN  in expandMOVImmSimple()  local
495     Shift = (TZ / 16) * 16;  in expandMOVImmSimple()
496     LastShift = ((63 - LZ) / 16) * 16;  in expandMOVImmSimple()
498   unsigned Imm16 = (Imm >> Shift) & Mask;  in expandMOVImmSimple()
501                    AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });  in expandMOVImmSimple()
503   if (Shift == LastShift)  in expandMOVImmSimple()
512   while (Shift < LastShift) {  in expandMOVImmSimple()
513     Shift += 16;  in expandMOVImmSimple()
514     Imm16 = (Imm >> Shift) & Mask;  in expandMOVImmSimple()
516       continue; // This 16-bit portion is already set correctly.  in expandMOVImmSimple()
519                      AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });  in expandMOVImmSimple()
522   // Now, we get 16-bit divided Imm. If high and low bits are same in  in expandMOVImmSimple()
523   // 32-bit, there is an opportunity to reduce instruction.  in expandMOVImmSimple()
525     for (int Size = Insn.size(); Size > 2; Size--)  in expandMOVImmSimple()
532 /// real move-immediate instructions to synthesize the immediate.
537   // Scan the immediate and count the number of 16-bit chunks which are either  in expandMOVImm()
541   for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {  in expandMOVImm()  local
542     const unsigned Chunk = (Imm >> Shift) & Mask;  in expandMOVImm()
550   if ((BitSize / 16) - OneChunks <= 1 || (BitSize / 16) - ZeroChunks <= 1) {  in expandMOVImm()
556   uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);  in expandMOVImm()
568   if (OneChunks >= (BitSize / 16) - 2 || ZeroChunks >= (BitSize / 16) - 2) {  in expandMOVImm()
573   assert(BitSize == 64 && "All 32-bit immediates can be expanded with a"  in expandMOVImm()
576   // Try other two-instruction sequences.  in expandMOVImm()
578   // 64-bit ORR followed by MOVK.  in expandMOVImm()
581   // be replaced with ones, or we take the bit pattern from the other half of  in expandMOVImm()
582   // the 64-bit immediate. This is comprehensive because of the way ORR  in expandMOVImm()
584   for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {  in expandMOVImm()  local
585     uint64_t ShiftedMask = (0xFFFFULL << Shift);  in expandMOVImm()
594       // Create the ORR-immediate instruction.  in expandMOVImm()
598       const unsigned Imm16 = getChunk(UImm, Shift / 16);  in expandMOVImm()
600 		       AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });  in expandMOVImm()
605   // Attempt to use a sequence of two ORR-immediate instructions.  in expandMOVImm()
609   // Attempt to use a sequence of ORR-immediate followed by AND-immediate.  in expandMOVImm()
613   // Attempt to use a sequence of ORR-immediate followed by EOR-immediate.  in expandMOVImm()
617   // FIXME: Add more two-instruction sequences.  in expandMOVImm()
624   // four-instruction sequence, but we won't worry about that for now.)  in expandMOVImm()
630   // Check for identical 16-bit chunks within the constant and if so materialize  in expandMOVImm()
631   // them with a single ORR instruction. The remaining one or two 16-bit chunks  in expandMOVImm()
645   // four-instruction sequence.  in expandMOVImm()