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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-single.txt1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
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H A Dbrcm,bcm2835-gpio.txt7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
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H A Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
25 - enum:
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H A Datmel,at91rm9200-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manikandan Muralidharan <manikandan.m@microchip.com>
22 - items:
23 - enum:
24 - atmel,at91rm9200-pinctrl
25 - atmel,at91sam9x5-pinctrl
26 - atmel,sama5d3-pinctrl
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H A Datmel,at91-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
15 used for a specific device or function. This node represents both mux and config
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl"
24 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
43 configured in it by putting 1 to the pin bit (1 << pin)
46 From the datasheet Table 10-2.
84 - atmel,pins: 4 integers array, represents a group of pins mux and config
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
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H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
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H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
20 clock-output-names = "adc_tsc_fck";
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H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
26 ti,max-div = <3>;
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H A Domap3-gta04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on omap3-beagle-xm.dts
7 /dts-v1/;
10 #include <dt-bindings/input/input.h>
17 cpu0-supply = <&vcc>;
27 stdout-pat
668 #define BIT( global() macro
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/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416_gpio.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
32 * Configure GPIO Output Mux control
43 /* each MUX controls 6 GPIO pins */ in cfgOutputMux()
52 * 5 bits per GPIO pin. Bits 0..4 for 1st pin in that mux, in cfgOutputMux()
58 * From Owl to Merlin 1.0, the value read from MUX1 bit 4 to bit in cfgOutputMux()
62 * <==== Bit 4 is used by both gpio_output_mux[0] [1]. in cfgOutputMux()
63 * Currently the max value for gpio_output_mux[] is 6. So bit 4 in cfgOutputMux()
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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H A Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dbrcm,bcm7120-l2-intc.txt1 Broadcom BCM7120-style Level 2 interrupt controller
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
9 - outputs multiple interrupts signals towards its interrupt controller parent
11 - controls how some of the interrupts will be flowing, whether they will
16 - has one 32-bit enable word and one 32-bit status word
18 - no atomic set/clear operations
20 - not all bits within the interrupt controller actually map to an interrupt
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
27 \-----------\
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
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H A Dbrcm,bcm7120-l2-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controlle
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Domap-gpmc.txt7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_gpio.c33 * Configure GPIO Output Mux control
87 /* each MUX controls 6 GPIO pins */ in ar9300_gpio_cfg_output_mux()
97 * 5 bits per GPIO pin. in ar9300_gpio_cfg_output_mux()
98 * Bits 0..4 for 1st pin in that mux, in ar9300_gpio_cfg_output_mux()
163 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); in ar9300_gpio_cfg_output()
170 /* Convert HAL signal type definitions to hardware-specific values. */ in ar9300_gpio_cfg_output()
222 /* Configure the MUX */ in ar9300_gpio_cfg_output()
226 /* 2 bits per output mode */ in ar9300_gpio_cfg_output()
237 * Configure GPIO Output lines -LED off
287 HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins); in ar9300_gpio_cfg_output_led_off()
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/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dti,pruss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dgpmc-nand.txt7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
23 - nand-bus-width: Set this numeric value to 16 if the hardware
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
30 "hw-romcode" <deprecated> use "ham1" instead
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/freebsd/sys/dev/dpaa2/
H A Ddpaa2_ni_dpkg.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause
4 * Copyright © 2013-2015 Freescale Semiconductor, Inc.
41 * Copyright © 2021-2022 Dmitry Salychev
68 #define BIT(x) (1ul << (x)) macro
71 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
76 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
81 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
93 * enum dpkg_extract_type - Enumeration for selecting extraction type
96 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
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/freebsd/sys/arm/ti/
H A Dti_pinmux.c34 * Exposes pinmux module to pinctrl-compatible interface
67 { -1, 0 }
73 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg))
75 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
77 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
79 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
82 * ti_padconf_devmap - Array of pins, should be defined one per SoC
91 * ti_pinmux_padconf_from_name - searches the list of pads and returns entry
103 padconf = ti_pinmux_dev->padconf; in ti_pinmux_padconf_from_name()
104 while (padconf->ballname != NULL) { in ti_pinmux_padconf_from_name()
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/freebsd/sys/arm/freescale/vybrid/
H A Dvf_sai.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
83 #define TCR2_BCP (1 << 25) /* Bit Clock Polarity */
84 #define TCR2_BCD (1 << 24) /* Bit Clock Direction */
94 #define TCR5_FBT_M 0x1f /* First Bit Shifted */
95 #define TCR5_FBT_S 8 /* First Bit Shifted */
101 #define TCSR_BCE (1 << 28) /* Bit Clock Enable */
110 uint32_t div; /* Bit Clock Divide. Division value is (div + 1) * 2. */
117 * Bit clock divider formula
120 * MCLK - master clock
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/freebsd/sys/contrib/device-tree/src/arm/nxp/mxs/
H A Dimx28-cfa10049.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
8 * need to include the CFA-10036 DTS.
10 #include "imx28-cfa10036.dts"
13 model = "Crystalfontz CFA-1004
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/freebsd/sys/contrib/device-tree/src/mips/ralink/
H A Dmt7628a.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7628a-soc";
9 #address-cells = <1>;
10 #size-cells = <0>;
19 resetc: reset-controller {
20 compatible = "ralink,rt2880-reset";
21 #reset-cells = <1>;
24 cpuintc: interrupt-controller {
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/freebsd/sys/dev/iicbus/adc/
H A Dads111x.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
55 * Chip registers, bit definitions, shifting and masking values.
61 #define ADS111x_CONF_MUX_SHIFT 12 /* Input mux setting */
72 * On config write, the operational-state bit starts a measurement, on read it
79 * The default values for config items that are not per-channel. Mostly, this
90 * Per-channel defaults. The chip only has one control register, and we load
91 * per-channel values into it every time we make a measurement on that channel.
93 * values we maintain on a per-channel basis.
99 * Full-scale ranges for each available amplifier setting, in microvolts. The
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