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/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	uncore-io.json	87 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 97 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 107 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 117 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 127 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 137 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 147 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 157 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 167 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 177 …s being used at this ring stop. This includes when packets are passing by and when packets are be… [all …]
H A D	uncore-cache.json	224 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 234 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 244 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 254 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 264 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 274 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 284 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 294 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 304 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 314 …s being used at this ring stop. This includes when packets are passing by and when packets are be… [all …]
H A D	memory.json	11 "BriefDescription": "Loads with latency value being above 128", 18 "PublicDescription": "Loads with latency value being above 128.", 23 "BriefDescription": "Loads with latency value being above 16", 30 "PublicDescription": "Loads with latency value being above 16.", 35 "BriefDescription": "Loads with latency value being above 256", 42 "PublicDescription": "Loads with latency value being above 256.", 47 "BriefDescription": "Loads with latency value being above 32", 54 "PublicDescription": "Loads with latency value being above 32.", 59 "BriefDescription": "Loads with latency value being above 4", 66 "PublicDescription": "Loads with latency value being above 4.", [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	uncore-io.json	113 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 123 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 133 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 143 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 153 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 163 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 173 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 203 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 213 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 223 …s being used at this ring stop. This includes when packets are passing by and when packets are be… [all …]
H A D	frontend.json	15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", 72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 87 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 110 "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", 119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 124 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", 129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", 138 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivere [all...]
H A D	uncore-cache.json	475 "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", 485 "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX-- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", 495 "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.", 505 "PublicDescription": "Counts the number of cycles that the AD ring is being use [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	uncore-io.json	113 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 123 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 133 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 143 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 153 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 163 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 173 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 203 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 213 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 223 …s being used at this ring stop. This includes when packets are passing by and when packets are be… [all …]
H A D	memory.json	85 "BriefDescription": "Randomly selected loads with latency value being above 128", 94 "PublicDescription": "Counts randomly selected loads with latency value being above 128.", 99 "BriefDescription": "Randomly selected loads with latency value being above 16", 108 "PublicDescription": "Counts randomly selected loads with latency value being above 16.", 113 "BriefDescription": "Randomly selected loads with latency value being above 256", 122 "PublicDescription": "Counts randomly selected loads with latency value being above 256.", 127 "BriefDescription": "Randomly selected loads with latency value being above 32", 136 "PublicDescription": "Counts randomly selected loads with latency value being above 32.", 141 "BriefDescription": "Randomly selected loads with latency value being above 4", 150 "PublicDescription": "Counts randomly selected loads with latency value being abov [all...]
H A D	frontend.json	15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", 72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 87 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 110 "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", 119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 124 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", 129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", 138 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivere [all...]
H A D	uncore-cache.json	281 "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", 291 "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", 301 "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", 311 "PublicDescription": "Counts the number of cycles that the AD ring is being use [all...]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	uncore-io.json	113 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 123 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 133 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 143 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 153 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 163 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 193 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 203 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 213 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 223 …s being used at this ring stop. This includes when packets are passing by and when packets are be… [all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	uncore-io.json	107 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 117 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 127 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 137 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 147 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 157 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 167 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 177 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 187 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 197 …s being used at this ring stop. This includes when packets are passing by and when packets are be… [all …]
H A D	uncore-cache.json	161 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 171 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 181 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 191 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 201 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 211 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 221 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 231 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 241 …s being used at this ring stop. This includes when packets are passing by and when packets are be… 251 …s being used at this ring stop. This includes when packets are passing by and when packets are be… [all …]
H A D	uncore-memory.json	282 …being throttled by either thermal constraints or by the PCU throttling. It is not possible to dis… 292 …being throttled by either thermal constraints or by the PCU throttling. It is not possible to dis… 302 …being throttled by either thermal constraints or by the PCU throttling. It is not possible to dis… 312 …being throttled by either thermal constraints or by the PCU throttling. It is not possible to dis… 322 …being throttled by either thermal constraints or by the PCU throttling. It is not possible to dis… 332 …being throttled by either thermal constraints or by the PCU throttling. It is not possible to dis… 342 …being throttled by either thermal constraints or by the PCU throttling. It is not possible to dis… 352 …being throttled by either thermal constraints or by the PCU throttling. It is not possible to dis… 411 …he memory controller, and need credits for an entry in this buffer before being sent from the HA t… 420 …he memory controller, and need credits for an entry in this buffer before being sent from the HA t… [all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	memory.json	11 "BriefDescription": "Loads with latency value being above 128", 18 "PublicDescription": "Loads with latency value being above 128.", 23 "BriefDescription": "Loads with latency value being above 16", 30 "PublicDescription": "Loads with latency value being above 16.", 35 "BriefDescription": "Loads with latency value being above 256", 42 "PublicDescription": "Loads with latency value being above 256.", 47 "BriefDescription": "Loads with latency value being above 32", 54 "PublicDescription": "Loads with latency value being above 32.", 59 "BriefDescription": "Loads with latency value being above 4", 66 "PublicDescription": "Loads with latency value being above 4.", [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A D	branch.json	18 …still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off", 21 … still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off" 24 … the address. This event still counts when branch prediction is disabled due to the MMU being off", 27 …r the address. This event still counts when branch prediction is disabled due to the MMU being off" 30 … the address. This event still counts when branch prediction is disabled due to the MMU being off", 33 …d the address. This event still counts when branch prediction is disabled due to the MMU being off" 36 …This event still counts when branch prediction is disabled due to the MMU being off. Conditional i… 39 …This event still counts when branch prediction is disabled due to the MMU being off. Conditional i… 42 …he condition. This event still counts when branch prediction is disabled due to the MMU being off", 45 …the condition. This event still counts when branch prediction is disabled due to the MMU being off" [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A D	branch.json	18 …r is retired. This event still counts when branch prediction is disabled due to the MMU being off", 21 …or is retired. This event still counts when branch prediction is disabled due to the MMU being off" 24 … the address. This event still counts when branch prediction is disabled due to the MMU being off", 27 …r the address. This event still counts when branch prediction is disabled due to the MMU being off" 30 … the address. This event still counts when branch prediction is disabled due to the MMU being off", 33 …d the address. This event still counts when branch prediction is disabled due to the MMU being off" 36 …This event still counts when branch prediction is disabled due to the MMU being off. Conditional i… 39 …This event still counts when branch prediction is disabled due to the MMU being off. Conditional i… 42 …he condition. This event still counts when branch prediction is disabled due to the MMU being off", 45 …the condition. This event still counts when branch prediction is disabled due to the MMU being off" [all …]
H A D	pipeline.json	9 …ent counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed", 12 …vent counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed" 15 …nt counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed", 18 …ent counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed" 21 …This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed", 24 ….This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed" 57 …Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)", 60 … Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)" 69 … cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full", 72 …y cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full"
/linux/kernel/bpf/
H A D	cpumask.c	23 * not being defined, the structure is the same size regardless. 72 * @cpumask: The BPF cpumask being acquired. The cpumask must be a trusted 91 * @cpumask: The cpumask being released. in bpf_cpumask_release() 113 * @cpumask: The cpumask being queried. in bpf_cpumask_first() 129 * @cpumask: The cpumask being queried. 163 * @cpumask: The BPF cpumask in which a bit is being set. in bpf_cpumask_clear_cpu() 176 * @cpumask: The BPF cpumask in which a bit is being cleared. 188 * @cpu: The CPU being queried for. 189 * @cpumask: The cpumask being queried for containing a CPU. 205 * @cpu: The CPU being se [all...]
/linux/crypto/asymmetric_keys/
H A D	restrict.c	55 * @dest_keyring: Keyring being linked to. 56 * @type: The type of key being added. 62 * new certificate as being trusted. 117 * @dest_keyring: Keyring being linked to. 118 * @type: The type of key being added. 123 * certificate as being ok to link. 157 * @dest_keyring: Keyring being linked to. 158 * @type: The type of key being added. 163 * then mark the new certificate as being ok to link. Afterwards verify 250 * one that is being considered for addition to in key_or_keyring_common() [all …]
/linux/certs/
H A D	system_keyring.c	37 * @dest_keyring: Keyring being linked to. 38 * @type: The type of key being added. 43 * being vouched for by a key in the built in system keyring. 56 * @dest_keyring: Keyring being linked to. 57 * @type: The type of key being added. 62 * being vouched for by a key in the built in system keyring. The new key 78 * @dest_keyring: Keyring being linked to. 79 * @type: The type of key being added. 84 * being vouched for by a key in either the built-in or the secondary system 108 * @dest_keyring: Keyring being linked to. [all …]
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A D	frontend.json	15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", 72 "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 82 "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 87 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 92 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", 110 "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", 119 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 124 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", 129 "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", 138 "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivere [all...]
/linux/fs/crypto/
H A D	hooks.c	12 * @inode: the inode being opened 13 * @filp: the struct file being set up 21 * is being opened) is encrypted, then the inode being opened uses the same 46 * with a lightweight RCU-mode check for the parent directory being in fscrypt_file_open() 79 * available, as it's implied by the dentry not being a no-key name. in __fscrypt_prepare_link() 98 * available, as it's implied by the dentries not being no-key names. in __fscrypt_prepare_rename() 133 * @dir: the encrypted directory being searched 134 * @dentry: the dentry being looked up in @dir 143 * Return: 0 on success; -errno on error. Note that the encryption key being 146 * like the key being unavailable, so that files can still be deleted. [all …]
/linux/Documentation/ABI/testing/
H A D	configfs-most	`44 collected from the network before being 61 a physical device is being attached to the bus. 99 collected from the network before being 116 a physical device is being attached to the bus. 154 collected from the network before being 171 a physical device is being attached to the bus. 220 collected from the network before being 237 a physical device is being attached to the bus.`
/linux/include/linux/
H A D	llist.h	18 * if a preemption happens in the middle of the delete operation and on being 33 * operation, with "-" being no lock needed, while "L" being lock is needed. 135 * safely only after being deleted from list, so start with an entry 138 * If being used on entries deleted from lock-less list directly, the 154 * safely only after being deleted from list, so start with an entry 157 * If being used on entries deleted from lock-less list directly, the 172 * safely only after being removed from list, so start with an entry 175 * If being used on entries deleted from lock-less list directly, the 194 * safely only after being removed from list, so start with an entry 197 * If being used on entries deleted from lock-less list directly, the [all …]

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