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Searched +full:bcm2836 +full:- +full:l1 +full:- +full:intc (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dbrcm,bcm2836-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2836-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2836 per-CPU interrupt controller
10 - Stefan Wahren <wahrenst@gmx.net>
11 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
14 The BCM2836 has a per-cpu interrupt controller for the timer, PMU
16 peripheral (GPU) events, which chain to the BCM2835-style interrupt
20 - $ref: /schemas/interrupt-controller.yaml#
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/linux/drivers/irqchip/
H A Dirq-bcm2836.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
14 #include <linux/irqchip/irq-bcm2836.h>
23 static struct bcm2836_arm_irqchip_intc intc __read_mostly;
29 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_mask_per_cpu_irq()
38 void __iomem *reg = intc.base + reg_offset + 4 * cpu; in bcm2836_arm_irqchip_unmask_per_cpu_irq()
46 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_mask_timer_irq()
53 d->hwirq - LOCAL_IRQ_CNTPSIRQ, in bcm2836_arm_irqchip_unmask_timer_irq()
58 .name = "bcm2836-timer",
66 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR); in bcm2836_arm_irqchip_mask_pmu_irq()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
6 compatible = "brcm,bcm2836";
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
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H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 local_intc: interrupt-controller@40000000 {
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
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H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
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/linux/arch/arm/mach-bcm/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2015 Broadcom Corporation
12 #include <linux/irqchip/irq-bcm2836.h>
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
54 return -ENXIO; in scu_a9_enable()
61 return -ENOENT; in scu_a9_enable()
68 return -ENOMEM; in scu_a9_enable()
106 return -EINVAL; in nsp_write_lut()
111 pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu); in nsp_write_lut()
112 return -ENOMEM; in nsp_write_lut()
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