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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dcirrus,lochnagar.yaml86 gf-gpio2, gf-gpio3, gf-gpio7, codec-aif1-bclk,
88 codec-aif2-bclk, codec-aif2-rxdat, codec-aif2-lrclk,
89 codec-aif2-txdat, codec-aif3-bclk, codec-aif3-rxdat,
90 codec-aif3-lrclk, codec-aif3-txdat, dsp-aif1-bclk,
92 dsp-aif2-bclk, dsp-aif2-rxdat, dsp-aif2-lrclk,
93 dsp-aif2-txdat, psia1-bclk, psia1-rxdat, psia1-lrclk,
94 psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk,
95 psia2-txdat, gf-aif3-bclk, gf-aif3-rxdat,
96 gf-aif3-lrclk, gf-aif3-txdat, gf-aif4-bclk,
98 gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk,
[all …]
/linux/drivers/media/dvb-frontends/
H A Dz0194a.h16 u8 bclk = 0; in sharp_z0194a_set_symbol_rate() local
19 aclk = 0xb7; bclk = 0x47; } in sharp_z0194a_set_symbol_rate()
21 aclk = 0xb7; bclk = 0x4b; } in sharp_z0194a_set_symbol_rate()
23 aclk = 0xb7; bclk = 0x4f; } in sharp_z0194a_set_symbol_rate()
25 aclk = 0xb7; bclk = 0x53; } in sharp_z0194a_set_symbol_rate()
27 aclk = 0xb6; bclk = 0x53; } in sharp_z0194a_set_symbol_rate()
29 aclk = 0xb4; bclk = 0x51; } in sharp_z0194a_set_symbol_rate()
32 stv0299_writereg(fe, 0x14, bclk); in sharp_z0194a_set_symbol_rate()
H A Dbsbe1.h37 u8 bclk = 0; in alps_bsbe1_set_symbol_rate() local
39 if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; } in alps_bsbe1_set_symbol_rate()
40 else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; } in alps_bsbe1_set_symbol_rate()
41 else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; } in alps_bsbe1_set_symbol_rate()
42 else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; } in alps_bsbe1_set_symbol_rate()
43 else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; } in alps_bsbe1_set_symbol_rate()
44 else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; } in alps_bsbe1_set_symbol_rate()
47 stv0299_writereg(fe, 0x14, bclk); in alps_bsbe1_set_symbol_rate()
H A Dbsru6.h56 u8 bclk = 0; in alps_bsru6_set_symbol_rate() local
60 bclk = 0x47; in alps_bsru6_set_symbol_rate()
63 bclk = 0x4b; in alps_bsru6_set_symbol_rate()
66 bclk = 0x4f; in alps_bsru6_set_symbol_rate()
69 bclk = 0x53; in alps_bsru6_set_symbol_rate()
72 bclk = 0x53; in alps_bsru6_set_symbol_rate()
75 bclk = 0x51; in alps_bsru6_set_symbol_rate()
79 stv0299_writereg(fe, 0x14, bclk); in alps_bsru6_set_symbol_rate()
/linux/drivers/media/pci/mantis/
H A Dmantis_vp1033.c110 u8 bclk = 0; in lgtdqcs001f_set_symbol_rate() local
114 bclk = 0x47; in lgtdqcs001f_set_symbol_rate()
117 bclk = 0x4b; in lgtdqcs001f_set_symbol_rate()
120 bclk = 0x4f; in lgtdqcs001f_set_symbol_rate()
123 bclk = 0x53; in lgtdqcs001f_set_symbol_rate()
126 bclk = 0x53; in lgtdqcs001f_set_symbol_rate()
129 bclk = 0x51; in lgtdqcs001f_set_symbol_rate()
132 stv0299_writereg(fe, 0x14, bclk); in lgtdqcs001f_set_symbol_rate()
/linux/Documentation/sound/soc/
H A Ddai.rst15 The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
27 Rx lines are used for audio transmission, while the bit clock (BCLK) and
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
38 MSB is transmitted on the falling edge of the first BCLK after LRC
51 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
61 MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
/linux/include/sound/sof/
H A Ddai.h35 #define SOF_DAI_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */
36 #define SOF_DAI_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */
37 #define SOF_DAI_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */
39 #define SOF_DAI_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */
40 #define SOF_DAI_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */
41 #define SOF_DAI_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */
42 #define SOF_DAI_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */
H A Ddai-intel.h45 /* bclk keep active */
49 /* bclk idle */
53 /* bclk early start */
69 uint32_t bclk_rate; /* bclk frequency in Hz */
88 uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK
H A Ddai-imx.h24 uint32_t bclk_rate; /* BCLK frequency in Hz */
45 uint32_t bclk_rate; /* BCLK frequency in Hz */
/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy_8996.c128 static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk, in pll_get_integloop_gain() argument
131 int digclk_divsel = bclk >= HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2; in pll_get_integloop_gain()
166 static int pll_get_post_div(struct hdmi_8996_post_divider *pd, u64 bclk) in pll_get_post_div() argument
185 vco = bclk >> half_rate_mode; in pll_get_post_div()
222 u64 bclk; in pll_calculate() local
237 bclk = ((u64)pix_clk) * 10; in pll_calculate()
239 if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) in pll_calculate()
244 ret = pll_get_post_div(&pd, bclk); in pll_calculate()
262 integloop_gain = pll_get_integloop_gain(frac_start, bclk, in pll_calculate()
285 if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) in pll_calculate()
[all …]
H A Dhdmi_phy_8998.c127 static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk, in pll_get_integloop_gain() argument
130 int digclk_divsel = bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2; in pll_get_integloop_gain()
158 static int pll_get_post_div(struct hdmi_8998_post_divider *pd, u64 bclk) in pll_get_post_div() argument
184 u64 freq = div_u64(bclk, (1 << half_rate_mode)); in pll_get_post_div()
286 u64 bclk; in pll_calculate() local
300 bclk = ((u64)pix_clk) * 10; in pll_calculate()
302 ret = pll_get_post_div(&pd, bclk); in pll_calculate()
320 integloop_gain = pll_get_integloop_gain(frac_start, bclk, in pll_calculate()
329 if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) in pll_calculate()
350 cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x5 : 0x4; in pll_calculate()
[all …]
/linux/drivers/staging/greybus/
H A Daudio_apbridgea.h13 * - the DSP on the MSM8994 is the clock master for MCLK, BCLK, and WCLK
14 * - WCLK changes on the falling edge of BCLK
16 * - TX data is sent on the falling edge of BCLK
17 * - RX data is received/latched on the rising edge of BCLK
/linux/drivers/iommu/
H A Dmtk_iommu_v1.c110 struct clk *bclk; member
542 ret = clk_prepare_enable(data->bclk); in mtk_iommu_v1_hw_init()
544 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); in mtk_iommu_v1_hw_init()
570 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_hw_init()
638 data->bclk = devm_clk_get(dev, "bclk"); in mtk_iommu_v1_probe()
639 if (IS_ERR(data->bclk)) in mtk_iommu_v1_probe()
640 return PTR_ERR(data->bclk); in mtk_iommu_v1_probe()
700 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_probe()
711 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_remove()
/linux/sound/soc/atmel/
H A Datmel_ssc_dai.h29 #define ATMEL_SSC_CMR_DIV 0 /* MCK divider for BCLK */
30 #define ATMEL_SSC_TCMR_PERIOD 1 /* BCLK divider for transmit FS */
31 #define ATMEL_SSC_RCMR_PERIOD 2 /* BCLK divider for receive FS */
H A Dmchp-i2s-mcc.c426 unsigned int bclk, unsigned int *mra, in mchp_i2s_mcc_config_divs() argument
438 sysclk = bclk; in mchp_i2s_mcc_config_divs()
444 * BCLK is Selected CLK / (2 * ISCKDIV); in mchp_i2s_mcc_config_divs()
445 * if IMCKDIV or ISCKDIV are 0, MCLK or BCLK = Selected CLK in mchp_i2s_mcc_config_divs()
447 lcm_rate = lcm(sysclk, bclk); in mchp_i2s_mcc_config_divs()
449 (lcm_rate / bclk % 2 == 1 && lcm_rate / bclk > 2)) in mchp_i2s_mcc_config_divs()
454 (clk_rate == bclk || clk_rate / (bclk * 2) <= GENMASK(5, 0)); in mchp_i2s_mcc_config_divs()
498 *mra |= MCHP_I2SMCC_MRA_ISCKDIV(*best_rate / (2 * bclk)); in mchp_i2s_mcc_config_divs()
578 /* cpu is BCLK and LRC master */ in mchp_i2s_mcc_hw_params()
585 /* cpu is BCLK master */ in mchp_i2s_mcc_hw_params()
/linux/sound/hda/
H A Dhdac_i915.c21 * snd_hdac_i915_set_bclk - Reprogram BCLK for HSW/BDW
24 * Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
26 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
27 * BCLK = CDCLK * M / N
/linux/drivers/iio/adc/
H A Dstm32-adc-core.c91 * @bclk: bus clock common for all ADCs, depends on part used
109 struct clk *bclk; member
217 if (!priv->bclk) { in stm32h7_adc_clk_sel()
264 rate = clk_get_rate(priv->bclk); in stm32h7_adc_clk_sel()
270 duty = clk_get_scaled_duty_cycle(priv->bclk, 100); in stm32h7_adc_clk_sel()
560 ret = clk_prepare_enable(priv->bclk); in stm32_adc_core_hw_start()
577 clk_disable_unprepare(priv->bclk); in stm32_adc_core_hw_start()
596 clk_disable_unprepare(priv->bclk); in stm32_adc_core_hw_stop()
747 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus"); in stm32_adc_probe()
748 if (IS_ERR(priv->bclk)) in stm32_adc_probe()
[all …]
/linux/sound/soc/codecs/
H A Dwm5100.c1285 int lrclk, bclk, mask, base; in wm5100_set_fmt() local
1290 bclk = 0; in wm5100_set_fmt()
1312 bclk |= WM5100_AIF1_BCLK_MSTR; in wm5100_set_fmt()
1316 bclk |= WM5100_AIF1_BCLK_MSTR; in wm5100_set_fmt()
1328 bclk |= WM5100_AIF1_BCLK_INV; in wm5100_set_fmt()
1332 bclk |= WM5100_AIF1_BCLK_INV; in wm5100_set_fmt()
1342 WM5100_AIF1_BCLK_INV, bclk); in wm5100_set_fmt()
1405 int i, base, bclk, aif_rate, lrclk, wl, fl, sr; in wm5100_hw_params() local
1421 /* Target BCLK rate */ in wm5100_hw_params()
1422 bclk = snd_soc_params_to_bclk(params); in wm5100_hw_params()
[all …]
H A Dsma1303.c930 unsigned int bclk) in sma1303_setup_pll() argument
936 dev_dbg(component->dev, "%s : BCLK = %dHz\n", in sma1303_setup_pll()
937 __func__, bclk); in sma1303_setup_pll()
944 if (sma1303->pll_matches[i].input_clk == bclk) in sma1303_setup_pll()
986 unsigned int bclk = 0; in sma1303_dai_hw_params_amp() local
990 bclk = params_rate(params) * sma1303->frame_size; in sma1303_dai_hw_params_amp()
992 bclk = params_rate(params) * params_physical_width(params) in sma1303_dai_hw_params_amp()
1002 if (sma1303->last_bclk != bclk) { in sma1303_dai_hw_params_amp()
1003 sma1303_setup_pll(component, bclk); in sma1303_dai_hw_params_amp()
1004 sma1303->last_bclk = bclk; in sma1303_dai_hw_params_amp()
[all …]
/linux/sound/soc/
H A Dsoc-utils-test.c19 u32 bclk; member
21 /* rate fmt channels tdm_width tdm_slots slot_multiple bclk */
156 tdm_params_to_bclk_cases[i].bclk); in test_tdm_params_to_bclk()
169 tdm_params_to_bclk_cases[i].bclk); in test_tdm_params_to_bclk()
214 tdm_params_to_bclk_cases[i].bclk); in test_snd_soc_params_to_bclk()
/linux/drivers/media/common/b2c2/
H A Dflexcop-fe-tuner.c202 u8 bclk = 0; in samsung_tbmu24112_set_symbol_rate() local
205 aclk = 0xb7; bclk = 0x47; in samsung_tbmu24112_set_symbol_rate()
207 aclk = 0xb7; bclk = 0x4b; in samsung_tbmu24112_set_symbol_rate()
209 aclk = 0xb7; bclk = 0x4f; in samsung_tbmu24112_set_symbol_rate()
211 aclk = 0xb7; bclk = 0x53; in samsung_tbmu24112_set_symbol_rate()
213 aclk = 0xb6; bclk = 0x53; in samsung_tbmu24112_set_symbol_rate()
215 aclk = 0xb4; bclk = 0x51; in samsung_tbmu24112_set_symbol_rate()
219 stv0299_writereg(fe, 0x14, bclk); in samsung_tbmu24112_set_symbol_rate()
/linux/Documentation/devicetree/bindings/sound/
H A Dtas2552.txt18 tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
/linux/sound/soc/intel/boards/
H A Dsof_nau8825.c92 clk_freq = sof_dai_get_bclk(rtd); /* BCLK freq */ in sof_nau8825_hw_params()
95 dev_err(rtd->dev, "get bclk freq failed: %d\n", clk_freq); in sof_nau8825_hw_params()
103 dev_err(codec_dai->dev, "can't set BCLK clock %d\n", ret); in sof_nau8825_hw_params()
111 dev_err(codec_dai->dev, "can't set BCLK: %d\n", ret); in sof_nau8825_hw_params()
/linux/sound/soc/amd/
H A Dacp-da7219-max98357a.c80 da7219_dai_bclk = devm_clk_get(component->dev, "da7219-dai-bclk"); in cz_da7219_init()
113 * 48000. ADAU7002 spec: "The ADAU7002 requires a BCLK rate that is in da7219_clk_enable()
115 * source so for all codecs we have to limit bclk to 64X lrclk. in da7219_clk_enable()
162 rt5682_dai_bclk = devm_clk_get(component->dev, "rt5682-dai-bclk"); in cz_rt5682_init()
198 * 48000. ADAU7002 spec: "The ADAU7002 requires a BCLK rate that is in rt5682_clk_enable()
200 * source so for all codecs we have to limit bclk to 64X lrclk. in rt5682_clk_enable()
209 dev_err(rtd->dev, "Error setting bclk rate: %d\n", ret); in rt5682_clk_enable()
/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,r9a08g045-vbattb.yaml35 - const: bclk
77 clock-names = "bclk", "rtx";

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