| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | cirrus,lochnagar.yaml | 86 gf-gpio2, gf-gpio3, gf-gpio7, codec-aif1-bclk,
88 codec-aif2-bclk, codec-aif2-rxdat, codec-aif2-lrclk,
89 codec-aif2-txdat, codec-aif3-bclk, codec-aif3-rxdat,
90 codec-aif3-lrclk, codec-aif3-txdat, dsp-aif1-bclk,
92 dsp-aif2-bclk, dsp-aif2-rxdat, dsp-aif2-lrclk,
93 dsp-aif2-txdat, psia1-bclk, psia1-rxdat, psia1-lrclk,
94 psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk,
95 psia2-txdat, gf-aif3-bclk, gf-aif3-rxdat,
96 gf-aif3-lrclk, gf-aif3-txdat, gf-aif4-bclk,
98 gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk,
[all …]
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| /linux/drivers/media/dvb-frontends/ |
| H A D | z0194a.h | 16 u8 bclk = 0; in sharp_z0194a_set_symbol_rate() local
19 aclk = 0xb7; bclk = 0x47; } in sharp_z0194a_set_symbol_rate()
21 aclk = 0xb7; bclk = 0x4b; } in sharp_z0194a_set_symbol_rate()
23 aclk = 0xb7; bclk = 0x4f; } in sharp_z0194a_set_symbol_rate()
25 aclk = 0xb7; bclk = 0x53; } in sharp_z0194a_set_symbol_rate()
27 aclk = 0xb6; bclk = 0x53; } in sharp_z0194a_set_symbol_rate()
29 aclk = 0xb4; bclk = 0x51; } in sharp_z0194a_set_symbol_rate()
32 stv0299_writereg(fe, 0x14, bclk); in sharp_z0194a_set_symbol_rate()
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| H A D | bsbe1.h | 37 u8 bclk = 0; in alps_bsbe1_set_symbol_rate() local
39 if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; } in alps_bsbe1_set_symbol_rate()
40 else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; } in alps_bsbe1_set_symbol_rate()
41 else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; } in alps_bsbe1_set_symbol_rate()
42 else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; } in alps_bsbe1_set_symbol_rate()
43 else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; } in alps_bsbe1_set_symbol_rate()
44 else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; } in alps_bsbe1_set_symbol_rate()
47 stv0299_writereg(fe, 0x14, bclk); in alps_bsbe1_set_symbol_rate()
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| H A D | bsru6.h | 56 u8 bclk = 0; in alps_bsru6_set_symbol_rate() local
60 bclk = 0x47; in alps_bsru6_set_symbol_rate()
63 bclk = 0x4b; in alps_bsru6_set_symbol_rate()
66 bclk = 0x4f; in alps_bsru6_set_symbol_rate()
69 bclk = 0x53; in alps_bsru6_set_symbol_rate()
72 bclk = 0x53; in alps_bsru6_set_symbol_rate()
75 bclk = 0x51; in alps_bsru6_set_symbol_rate()
79 stv0299_writereg(fe, 0x14, bclk); in alps_bsru6_set_symbol_rate()
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| /linux/drivers/media/pci/mantis/ |
| H A D | mantis_vp1033.c | 110 u8 bclk = 0; in lgtdqcs001f_set_symbol_rate() local
114 bclk = 0x47; in lgtdqcs001f_set_symbol_rate()
117 bclk = 0x4b; in lgtdqcs001f_set_symbol_rate()
120 bclk = 0x4f; in lgtdqcs001f_set_symbol_rate()
123 bclk = 0x53; in lgtdqcs001f_set_symbol_rate()
126 bclk = 0x53; in lgtdqcs001f_set_symbol_rate()
129 bclk = 0x51; in lgtdqcs001f_set_symbol_rate()
132 stv0299_writereg(fe, 0x14, bclk); in lgtdqcs001f_set_symbol_rate()
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| /linux/Documentation/sound/soc/ |
| H A D | dai.rst | 15 The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
27 Rx lines are used for audio transmission, while the bit clock (BCLK) and
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
38 MSB is transmitted on the falling edge of the first BCLK after LRC
51 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
61 MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
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| /linux/include/sound/sof/ |
| H A D | dai.h | 35 #define SOF_DAI_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */
36 #define SOF_DAI_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */
37 #define SOF_DAI_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */
39 #define SOF_DAI_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */
40 #define SOF_DAI_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */
41 #define SOF_DAI_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */
42 #define SOF_DAI_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */
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| H A D | dai-intel.h | 45 /* bclk keep active */
49 /* bclk idle */
53 /* bclk early start */
69 uint32_t bclk_rate; /* bclk frequency in Hz */
88 uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK
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| H A D | dai-imx.h | 24 uint32_t bclk_rate; /* BCLK frequency in Hz */
45 uint32_t bclk_rate; /* BCLK frequency in Hz */
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| /linux/drivers/staging/greybus/ |
| H A D | audio_apbridgea.h | 13 * - the DSP on the MSM8994 is the clock master for MCLK, BCLK, and WCLK
14 * - WCLK changes on the falling edge of BCLK
16 * - TX data is sent on the falling edge of BCLK
17 * - RX data is received/latched on the rising edge of BCLK
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| /linux/drivers/iommu/ |
| H A D | mtk_iommu_v1.c | 110 struct clk *bclk; member
540 ret = clk_prepare_enable(data->bclk); in mtk_iommu_v1_hw_init()
542 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); in mtk_iommu_v1_hw_init()
568 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_hw_init()
635 data->bclk = devm_clk_get(dev, "bclk"); in mtk_iommu_v1_probe()
636 if (IS_ERR(data->bclk)) in mtk_iommu_v1_probe()
637 return PTR_ERR(data->bclk); in mtk_iommu_v1_probe()
697 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_probe()
708 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_remove()
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| /linux/sound/soc/atmel/ |
| H A D | atmel_ssc_dai.h | 29 #define ATMEL_SSC_CMR_DIV 0 /* MCK divider for BCLK */
30 #define ATMEL_SSC_TCMR_PERIOD 1 /* BCLK divider for transmit FS */
31 #define ATMEL_SSC_RCMR_PERIOD 2 /* BCLK divider for receive FS */
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| H A D | mchp-i2s-mcc.c | 426 unsigned int bclk, unsigned int *mra, in mchp_i2s_mcc_config_divs() argument
438 sysclk = bclk; in mchp_i2s_mcc_config_divs()
444 * BCLK is Selected CLK / (2 * ISCKDIV); in mchp_i2s_mcc_config_divs()
445 * if IMCKDIV or ISCKDIV are 0, MCLK or BCLK = Selected CLK in mchp_i2s_mcc_config_divs()
447 lcm_rate = lcm(sysclk, bclk); in mchp_i2s_mcc_config_divs()
449 (lcm_rate / bclk % 2 == 1 && lcm_rate / bclk > 2)) in mchp_i2s_mcc_config_divs()
454 (clk_rate == bclk || clk_rate / (bclk * 2) <= GENMASK(5, 0)); in mchp_i2s_mcc_config_divs()
498 *mra |= MCHP_I2SMCC_MRA_ISCKDIV(*best_rate / (2 * bclk)); in mchp_i2s_mcc_config_divs()
578 /* cpu is BCLK and LRC master */ in mchp_i2s_mcc_hw_params()
585 /* cpu is BCLK master */ in mchp_i2s_mcc_hw_params()
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| /linux/tools/power/cpupower/utils/ |
| H A D | cpufreq-info.c | 171 double bclk; in get_boost_mode_x86() local
177 bclk = 100.00; in get_boost_mode_x86()
179 bclk = 133.33; in get_boost_mode_x86()
181 dprint (" Ratio: 0x%llx - bclk: %f\n", in get_boost_mode_x86()
182 intel_turbo_ratio, bclk); in get_boost_mode_x86()
187 ratio * bclk); in get_boost_mode_x86()
192 ratio * bclk); in get_boost_mode_x86()
197 ratio * bclk); in get_boost_mode_x86()
202 ratio * bclk); in get_boost_mode_x86()
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| /linux/sound/soc/codecs/ |
| H A D | da7219.c | 802 struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX]; in da7219_dai_event() local
811 if (bclk) { in da7219_dai_event()
812 ret = clk_prepare_enable(bclk); in da7219_dai_event()
858 if (bclk) in da7219_dai_event()
859 clk_disable_unprepare(bclk); in da7219_dai_event()
1430 struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX]; in da7219_set_dai_tdm_slot() local
1475 if (bclk) { in da7219_set_dai_tdm_slot()
1478 ret = clk_set_rate(bclk, bclk_rate); in da7219_set_dai_tdm_slot()
1481 "Failed to set TDM BCLK rate %lu: %d\n", in da7219_set_dai_tdm_slot()
1566 struct clk *bclk = da7219->dai_clks[DA7219_DAI_BCLK_IDX]; in da7219_hw_params() local
[all …]
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| H A D | wm5100.c | 1285 int lrclk, bclk, mask, base; in wm5100_set_fmt() local
1290 bclk = 0; in wm5100_set_fmt()
1312 bclk |= WM5100_AIF1_BCLK_MSTR; in wm5100_set_fmt()
1316 bclk |= WM5100_AIF1_BCLK_MSTR; in wm5100_set_fmt()
1328 bclk |= WM5100_AIF1_BCLK_INV; in wm5100_set_fmt()
1332 bclk |= WM5100_AIF1_BCLK_INV; in wm5100_set_fmt()
1342 WM5100_AIF1_BCLK_INV, bclk); in wm5100_set_fmt()
1405 int i, base, bclk, aif_rate, lrclk, wl, fl, sr; in wm5100_hw_params() local
1421 /* Target BCLK rate */ in wm5100_hw_params()
1422 bclk = snd_soc_params_to_bclk(params); in wm5100_hw_params()
[all …]
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| H A D | max98373-i2c.c | 177 static int max98373_get_bclk_sel(int bclk) in max98373_get_bclk_sel() argument
182 if (bclk_sel_table[i] == bclk) in max98373_get_bclk_sel()
192 /* BCLK/LRCLK ratio calculation */ in max98373_set_clock()
197 /* BCLK configuration */ in max98373_set_clock()
333 /* BCLK configuration */ in max98373_dai_tdm_slot()
336 dev_err(component->dev, "BCLK %d not supported\n", in max98373_dai_tdm_slot()
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| H A D | sma1303.c | 930 unsigned int bclk) in sma1303_setup_pll() argument
936 dev_dbg(component->dev, "%s : BCLK = %dHz\n", in sma1303_setup_pll()
937 __func__, bclk); in sma1303_setup_pll()
944 if (sma1303->pll_matches[i].input_clk == bclk) in sma1303_setup_pll()
986 unsigned int bclk = 0; in sma1303_dai_hw_params_amp() local
990 bclk = params_rate(params) * sma1303->frame_size; in sma1303_dai_hw_params_amp()
992 bclk = params_rate(params) * params_physical_width(params) in sma1303_dai_hw_params_amp()
1002 if (sma1303->last_bclk != bclk) { in sma1303_dai_hw_params_amp()
1003 sma1303_setup_pll(component, bclk); in sma1303_dai_hw_params_amp()
1004 sma1303->last_bclk = bclk; in sma1303_dai_hw_params_amp()
[all …]
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| /linux/sound/hda/core/ |
| H A D | i915.c | 21 * snd_hdac_i915_set_bclk - Reprogram BCLK for HSW/BDW
24 * Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
26 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
27 * BCLK = CDCLK * M / N
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| /linux/sound/soc/ |
| H A D | soc-utils-test.c | 19 u32 bclk; member
21 /* rate fmt channels tdm_width tdm_slots slot_multiple bclk */
156 tdm_params_to_bclk_cases[i].bclk); in test_tdm_params_to_bclk()
169 tdm_params_to_bclk_cases[i].bclk); in test_tdm_params_to_bclk()
214 tdm_params_to_bclk_cases[i].bclk); in test_snd_soc_params_to_bclk()
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | tas2552.txt | 18 tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
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| /linux/drivers/media/common/b2c2/ |
| H A D | flexcop-fe-tuner.c | 202 u8 bclk = 0; in samsung_tbmu24112_set_symbol_rate() local
205 aclk = 0xb7; bclk = 0x47; in samsung_tbmu24112_set_symbol_rate()
207 aclk = 0xb7; bclk = 0x4b; in samsung_tbmu24112_set_symbol_rate()
209 aclk = 0xb7; bclk = 0x4f; in samsung_tbmu24112_set_symbol_rate()
211 aclk = 0xb7; bclk = 0x53; in samsung_tbmu24112_set_symbol_rate()
213 aclk = 0xb6; bclk = 0x53; in samsung_tbmu24112_set_symbol_rate()
215 aclk = 0xb4; bclk = 0x51; in samsung_tbmu24112_set_symbol_rate()
219 stv0299_writereg(fe, 0x14, bclk); in samsung_tbmu24112_set_symbol_rate()
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| /linux/sound/soc/intel/boards/ |
| H A D | sof_nau8825.c | 92 clk_freq = sof_dai_get_bclk(rtd); /* BCLK freq */ in sof_nau8825_hw_params()
95 dev_err(rtd->dev, "get bclk freq failed: %d\n", clk_freq); in sof_nau8825_hw_params()
103 dev_err(codec_dai->dev, "can't set BCLK clock %d\n", ret); in sof_nau8825_hw_params()
111 dev_err(codec_dai->dev, "can't set BCLK: %d\n", ret); in sof_nau8825_hw_params()
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| /linux/sound/soc/amd/acp/ |
| H A D | acp-mach-common.c | 78 clk_set_rate(drvdata->bclk, srate * bclk_ratio); in acp_clk_enable()
130 drvdata->bclk = clk_get(component->dev, "rt5682-dai-bclk"); in acp_card_rt5682_init()
301 /* Set tdm/i2s1 master bclk ratio */ in acp_card_rt5682_hw_params()
304 dev_err(rtd->dev, "Failed to set rt5682 tdm bclk ratio: %d\n", ret); in acp_card_rt5682_hw_params()
372 drvdata->bclk = clk_get(component->dev, "rt5682-dai-bclk"); in acp_card_rt5682s_init()
499 /* Set tdm/i2s1 master bclk ratio */ in acp_card_rt5682s_hw_params()
502 dev_err(rtd->dev, "Failed to set rt5682 tdm bclk ratio: %d\n", ret); in acp_card_rt5682s_hw_params()
507 clk_set_rate(drvdata->bclk, srate * ch * format); in acp_card_rt5682s_hw_params()
1356 * the lrck and bclk must be enabled brfore their all dapms be powered on, in acp_rtk_set_bias_level()
1364 /* Increase bclk's enable_count */ in acp_rtk_set_bias_level()
[all …]
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| /linux/sound/soc/amd/ |
| H A D | acp-da7219-max98357a.c | 80 da7219_dai_bclk = devm_clk_get(component->dev, "da7219-dai-bclk"); in cz_da7219_init()
113 * 48000. ADAU7002 spec: "The ADAU7002 requires a BCLK rate that is in da7219_clk_enable()
115 * source so for all codecs we have to limit bclk to 64X lrclk. in da7219_clk_enable()
162 rt5682_dai_bclk = devm_clk_get(component->dev, "rt5682-dai-bclk"); in cz_rt5682_init()
198 * 48000. ADAU7002 spec: "The ADAU7002 requires a BCLK rate that is in rt5682_clk_enable()
200 * source so for all codecs we have to limit bclk to 64X lrclk. in rt5682_clk_enable()
209 dev_err(rtd->dev, "Error setting bclk rate: %d\n", ret); in rt5682_clk_enable()
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