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/linux/drivers/clk/ux500/
H A Du8500_of_clk.c131 u32 bases[CLKRST_MAX]; in u8500_clk_init() local
144 for (i = 0; i < ARRAY_SIZE(bases); i++) { in u8500_clk_init()
151 bases[i] = r.start; in u8500_clk_init()
303 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
307 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
311 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
315 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
319 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
323 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
327 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
[all …]
H A Dreset-prcc.h13 * @base: the remapped PRCC bases
/linux/drivers/iommu/
H A Drockchip-iommu.c111 void __iomem **bases; member
352 writel(command, iommu->bases[i] + RK_MMU_COMMAND); in rk_iommu_command()
372 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); in rk_iommu_zap_lines()
382 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_stall_active()
394 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_paging_enabled()
406 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; in rk_iommu_is_reset_done()
431 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_stall()
452 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_stall()
473 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_paging()
494 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_paging()
[all …]
/linux/drivers/gpu/host1x/
H A Dsyncpt.c26 struct host1x_syncpt_base *bases = host->bases; in host1x_syncpt_base_request() local
30 if (!bases[i].requested) in host1x_syncpt_base_request()
36 bases[i].requested = true; in host1x_syncpt_base_request()
37 return &bases[i]; in host1x_syncpt_base_request()
282 struct host1x_syncpt_base *bases; in host1x_syncpt_init() local
291 bases = devm_kcalloc(host->dev, host->info->nb_bases, sizeof(*bases), in host1x_syncpt_init()
293 if (!bases) in host1x_syncpt_init()
302 bases[i].id = i; in host1x_syncpt_init()
306 host->bases = bases; in host1x_syncpt_init()
H A Ddev.h102 unsigned int nb_bases; /* host1x: number of syncpoint bases supported */
138 struct host1x_syncpt_base *bases; member
H A Dsyncpt.h62 /* Return number of wait bases supported. */
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dbase.c33 } bases[] = { in nv50_base_new() local
46 cid = nvif_mclass(&disp->disp->object, bases); in nv50_base_new()
52 return bases[cid].new(drm, head, bases[cid].oclass, pwndw); in nv50_base_new()
/linux/include/xen/interface/
H A Dmemory.h27 * OUT: MFN (*not* GMFN) bases of extents that were allocated
29 * IN: GMFN bases of extents to free
31 * IN: GPFN bases of extents to populate with memory
32 * OUT: GMFN bases of extents that were allocated
68 * [IN] Details of memory extents to be exchanged (GMFN bases).
80 * 4. @out.extent_start lists GPFN bases to be populated
81 * 5. @out.extent_start is overwritten with allocated GMFN bases
116 * Returns a list of MFN bases of 2MB extents comprising the machine_to_phys
/linux/include/linux/
H A Dposix-timers.h104 pct->bases[0].nextevt = U64_MAX; in posix_cputimers_init()
105 pct->bases[1].nextevt = U64_MAX; in posix_cputimers_init()
106 pct->bases[2].nextevt = U64_MAX; in posix_cputimers_init()
114 pct->bases[CPUCLOCK_SCHED].nextevt = runtime; in posix_cputimers_rt_watchdog()
137 .bases = INIT_CPU_TIMERBASES(s.posix_cputimers.bases), \
H A Dhrtimer_defs.h69 * struct hrtimer_cpu_base - the per cpu clock bases
70 * @lock: lock protecting the base and associated clock bases
73 * @active_bases: Bitfield to mark bases with active timers
95 * @clock_base: array of clock bases for this cpu
H A Dposix-timers_types.h48 * @bases: Base container for posix CPU clocks
57 struct posix_cputimer_base bases[CPUCLOCK_MAX]; member
/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-nvidia.c36 void __iomem *bases[MAX_SMMU_INSTANCES]; member
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
322 nvidia_smmu->bases[0] = smmu->base; in nvidia_smmu_impl_init()
330 nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res); in nvidia_smmu_impl_init()
331 if (IS_ERR(nvidia_smmu->bases[i])) in nvidia_smmu_impl_init()
332 return ERR_CAST(nvidia_smmu->bases[i]); in nvidia_smmu_impl_init()
/linux/kernel/time/
H A Dposix-cpu-timers.c28 pct->bases[CPUCLOCK_PROF].nextevt = cpu_limit * NSEC_PER_SEC; in posix_cputimers_group_init()
35 * tsk->signal->posix_cputimers.bases[clock].nextevt expiration cache if
154 return !(~pct->bases[CPUCLOCK_PROF].nextevt | in expiry_cache_is_inactive()
155 ~pct->bases[CPUCLOCK_VIRT].nextevt | in expiry_cache_is_inactive()
156 ~pct->bases[CPUCLOCK_SCHED].nextevt); in expiry_cache_is_inactive()
422 return tsk->posix_cputimers.bases + clkidx; in timer_base()
424 return tsk->signal->posix_cputimers.bases + clkidx; in timer_base()
542 cleanup_timerqueue(&pct->bases[CPUCLOCK_PROF].tqhead); in cleanup_timers()
543 cleanup_timerqueue(&pct->bases[CPUCLOCK_VIRT].tqhead); in cleanup_timers()
544 cleanup_timerqueue(&pct->bases[CPUCLOCK_SCHED].tqhead); in cleanup_timers()
[all …]
H A Dhrtimer.c65 * The timer bases:
67 * There are more clockids than hrtimer bases. Thus, we index
68 * into the timer bases by the hrtimer_base_type enum. When trying
542 * the clock bases so the result might be negative. Fix it up in __hrtimer_next_event_base()
557 * When a softirq is pending, we can ignore the HRTIMER_ACTIVE_SOFT bases,
559 * hrtimer_run_softirq(), hrtimer_update_softirq_timer() will re-add these bases.
561 * Therefore softirq values are those from the HRTIMER_ACTIVE_SOFT clock bases.
602 * soft bases. They will be handled in the already raised soft in hrtimer_update_next_event()
854 * clock bases and reprogram the clock event device. in hrtimer_reprogram()
877 * bases. Either it will see the update before handling a base or in update_needs_ipi()
[all …]
H A Dalarmtimer.c37 * struct alarm_base - Alarm timer bases
213 * When we are going into suspend, we look through the bases
856 * This function initializes the alarm bases and registers
866 /* Initialize alarm bases */ in alarmtimer_init()
/linux/arch/x86/boot/
H A Dearly_serial_console.c77 static const int bases[] = { 0x3f8, 0x2f8 }; in parse_earlyprintk() local
86 port = bases[idx]; in parse_earlyprintk()
/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_scaler.c155 static unsigned int bases[] = { in scaler_set_src_base() local
163 scaler_write(src_buf->dma_addr[i], bases[i]); in scaler_set_src_base()
218 static unsigned int bases[] = { in scaler_set_dst_base() local
226 scaler_write(dst_buf->dma_addr[i], bases[i]); in scaler_set_dst_base()
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek-hw.yaml25 Addresses and sizes for the memory of the HW bases in
/linux/drivers/sh/intc/
H A Dirqdomain.c59 * tree penalty for linear cases with non-zero hwirq bases. in intc_irq_domain_init()
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt6797.c17 * MT6797 have multiple bases to program pin configuration listed as the below:
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcik_regs.h26 /* if PTR32, these are the bases for scratch and lds */
/linux/drivers/staging/media/meson/vdec/
H A Dvdec_helpers.h16 * @reg_base: Registry bases of where to write the canvas indexes
/linux/Documentation/timers/
H A Dhighres.rst169 decision is made per timer base and synchronized across per-cpu timer bases in
171 clock event devices for the per-CPU timer bases, but currently only one
/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xxfb.h65 void __iomem *host; /* relocatable reg. bases */
/linux/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h93 * Internal memory bases and sizes
99 * External Static Memory Bank Address Space Bases
107 * External SDRAM Memory Bank Address Space Bases

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