| /linux/drivers/mfd/ |
| H A D | mcp-sa11x0.c | 29 void __iomem *base1; member
40 #define MCCR1(m) ((m)->base1 + 0x00)
196 m->base1 = ioremap(mem1->start, resource_size(mem1)); in mcp_sa11x0_probe()
197 if (!m->base0 || !m->base1) { in mcp_sa11x0_probe()
224 iounmap(m->base1); in mcp_sa11x0_probe()
249 iounmap(m->base1); in mcp_sa11x0_remove()
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| /linux/drivers/gpio/ |
| H A D | gpio-em.c | 25 void __iomem *base1; member
63 return ioread32(p->base1 + (offs - GIO_IDT0)); in em_gio_read()
72 iowrite32(value, p->base1 + (offs - GIO_IDT0)); in em_gio_write()
296 p->base1 = devm_platform_ioremap_resource(pdev, 1); in em_gio_probe()
297 if (IS_ERR(p->base1)) in em_gio_probe()
298 return PTR_ERR(p->base1); in em_gio_probe()
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| /linux/drivers/media/dvb-frontends/ |
| H A D | zl10039.c | 45 BASE1, enumerator
214 ret = zl10039_writereg(state, BASE1, 0x0A); in zl10039_set_params()
222 ret = zl10039_writereg(state, BASE1, 0x6A); in zl10039_set_params()
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| /linux/drivers/thermal/qcom/ |
| H A D | tsens.c | 77 u32 base1, base2; in tsens_read_calibration() local
96 ret = snprintf(name, sizeof(name), "base1%s", backup ? "_backup" : ""); in tsens_read_calibration()
100 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base1); in tsens_read_calibration()
135 p1[i] = p1[i] + (base1 << shift); in tsens_read_calibration()
145 p1[i] = (p1[i] + base1) << shift; in tsens_read_calibration()
212 u32 base1, base2; in tsens_read_calibration_legacy() local
221 base1 = tsens_read_cell(&format->base[0], format->base_len, cdata0, cdata1); in tsens_read_calibration_legacy()
232 p1[i] = p1[i] + (base1 << format->base_shift); in tsens_read_calibration_legacy()
240 p1[i] = (p1[i] + base1) << format->base_shift; in tsens_read_calibration_legacy()
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| H A D | tsens.h | 613 * @base: descriptors of the base0 and base1 fields
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| /linux/drivers/pinctrl/bcm/ |
| H A D | pinctrl-cygnus-mux.c | 92 * @base1: second I/O register base
104 void __iomem *base1; member
855 val = readl(pinctrl->base1 + mux->offset); in cygnus_gpio_request_enable()
857 writel(val, pinctrl->base1 + mux->offset); in cygnus_gpio_request_enable()
882 val = readl(pinctrl->base1 + mux->offset); in cygnus_gpio_disable_free()
884 writel(val, pinctrl->base1 + mux->offset); in cygnus_gpio_disable_free()
954 pinctrl->base1 = devm_platform_ioremap_resource(pdev, 1); in cygnus_pinmux_probe()
955 if (IS_ERR(pinctrl->base1)) { in cygnus_pinmux_probe()
957 return PTR_ERR(pinctrl->base1); in cygnus_pinmux_probe()
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| H A D | pinctrl-nsp-mux.c | 99 * @base1: second mux register
112 void __iomem *base1; member
429 base_address = pinctrl->base1; in nsp_pinmux_set()
575 pinctrl->base1 = devm_ioremap(&pdev->dev, res->start, in nsp_pinmux_probe()
577 if (!pinctrl->base1) { in nsp_pinmux_probe()
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| H A D | pinctrl-ns2-mux.c | 105 * @base1: second IOMUX register base
118 void __iomem *base1; member
613 base_address = pinctrl->base1; in ns2_pinmux_set()
1046 pinctrl->base1 = devm_ioremap(&pdev->dev, res->start, in ns2_pinmux_probe()
1048 if (!pinctrl->base1) { in ns2_pinmux_probe()
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| /linux/drivers/pinctrl/renesas/ |
| H A D | pinctrl-rzt2h.c | 94 void __iomem *base0, *base1; member
108 ((port) > RZT2H_MAX_SAFETY_PORTS ? (pctrl)->base0 : (pctrl)->base1)
1195 pctrl->base1 = devm_ioremap_resource(&pdev->dev, res); in rzt2h_pinctrl_cfg_regions()
1196 if (IS_ERR(pctrl->base1)) in rzt2h_pinctrl_cfg_regions()
1197 return PTR_ERR(pctrl->base1); in rzt2h_pinctrl_cfg_regions()
1203 writeb(0x0, pctrl->base1 + RSELP(port)); in rzt2h_pinctrl_cfg_regions()
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| /linux/drivers/pci/controller/ |
| H A D | pci-v3-semi.c | 264 * Base0 and Base1 can be used for any type of PCI memory access. Base2
362 * prefetchable), this frees up base1 for re-use by in v3_map_bus()
370 * Set up base1/map1 to point into configuration space. in v3_map_bus()
384 * Reassign base1 for use by prefetchable PCI memory in v3_unmap_bus()
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| /linux/drivers/video/ |
| H A D | aperture.c | 144 static bool overlap(resource_size_t base1, resource_size_t end1, in overlap() argument
147 return (base1 < end2) && (end1 > base2); in overlap()
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| /linux/drivers/net/wireless/marvell/mwifiex/ |
| H A D | sdio.c | 1450 u8 base0, base1; in mwifiex_prog_fw_w_helper() local
1501 &base1); in mwifiex_prog_fw_w_helper()
1504 "dev BASE1 register read failed:\t" in mwifiex_prog_fw_w_helper()
1505 "base1=%#04X(%d). Terminating dnld\n", in mwifiex_prog_fw_w_helper()
1506 base1, base1); in mwifiex_prog_fw_w_helper()
1509 len = (u16) (((base1 & 0xff) << 8) | (base0 & 0xff)); in mwifiex_prog_fw_w_helper()
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| /linux/arch/x86/hyperv/ |
| H A D | hv_vtl.c | 97 (desc->base1 << 16) | desc->base0; in hv_vtl_system_desc_base()
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| /linux/drivers/char/tpm/ |
| H A D | tpm_nsc.c | 366 dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n", in init_nsc()
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| /linux/tools/testing/selftests/kvm/include/x86/ |
| H A D | processor.h | 404 unsigned base1:8, type:4, s:1, dpl:2, p:1; member
434 (u64)desc->base1 << 16 | in get_desc64_base()
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| /linux/lib/zstd/compress/ |
| H A D | zstd_opt.c | 106 ZSTD_downscaleStats(unsigned* table, U32 lastEltIndex, U32 shift, base_directive_e base1) in ZSTD_downscaleStats() argument
113 unsigned const base = base1 ? 1 : (table[s]>0); in ZSTD_downscaleStats()
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| /linux/drivers/infiniband/hw/hfi1/ |
| H A D | pcie.c | 119 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); in hfi1_pcie_ddinit()
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| /linux/arch/x86/mm/ |
| H A D | fault.c | 500 addr = desc.base0 | (desc.base1 << 16) | ((unsigned long)desc.base2 << 24); in show_ldttss()
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| /linux/tools/testing/selftests/kvm/lib/x86/ |
| H A D | processor.c | 574 desc->base1 = segp->base >> 16; in kvm_seg_fill_gdt_64bit()
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| /linux/lib/ |
| H A D | test_bpf.c | 2208 * All patterns (base1, mask1) and (base2, mask2) bytes are tested.
2211 u8 base1, u8 mask1, in __bpf_fill_ld_imm64_bytes() argument
2233 byte = (base1 & mask1) | (rand & ~mask1); in __bpf_fill_ld_imm64_bytes()
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| /linux/Documentation/admin-guide/ |
| H A D | kernel-parameters.txt | 6572 Format: <base1>,<size1>[,<base2>,<size2>,...]
|