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/linux/arch/x86/kernel/cpu/mce/
H A Dintel.c27 * Also supports reliable discovery of shared banks.
36 * some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear()
37 * disables CMCI on all banks owned by the cpu and clears this bitfield. At
39 * taking ownership of some of the shared MCA banks that were previously
78 static bool cmci_supported(int *banks) in cmci_supported() argument
98 *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); in cmci_supported()
183 /* Skip banks in firmware first mode */ in cmci_skip_bank()
241 storm->banks[bank].poll_only = true; in cmci_claim_bank()
257 * We are able to set thresholds for some banks that in cmci_claim_bank()
272 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm64.c91 /* pin banks of exynos2200 pin-controller - ALIVE */
103 /* pin banks of exynos2200 pin-controller - CMGP */
130 /* pin banks of exynos2200 pin-controller - HSI1 */
135 /* pin banks of exynos2200 pin-controller - UFS */
140 /* pin banks of exynos2200 pin-controller - HSI1UFS */
145 /* pin banks of exynos2200 pin-controller - PERIC0 */
159 /* pin banks of exynos2200 pin-controller - PERIC1 */
167 /* pin banks of exynos2200 pin-controller - PERIC2 */
186 /* pin banks of exynos2200 pin-controller - VTS */
259 /* pin banks of exynos5433 pin-controller - ALIVE */
[all …]
H A Dpinctrl-exynos-arm.c103 /* pin banks of s5pv210 pin-controller */
105 /* Must start with EINTG banks, ordered by EINT group number. */
164 /* pin banks of exynos3250 pin-controller 0 */
166 /* Must start with EINTG banks, ordered by EINT group number. */
176 /* pin banks of exynos3250 pin-controller 1 */
178 /* Must start with EINTG banks, ordered by EINT group number. */
198 * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle
251 /* pin banks of exynos4210 pin-controller 0 */
253 /* Must start with EINTG banks, ordered by EINT group number. */
272 /* pin banks of exynos4210 pin-controller 1 */
[all …]
/linux/arch/arm/mach-omap2/
H A Dpowerdomains7xx_data.c37 .banks = 4,
78 .banks = 2,
92 .banks = 1,
105 .banks = 2,
119 .banks = 1,
132 .banks = 1,
144 .banks = 5,
170 .banks = 1,
186 .banks = 1,
201 .banks = 1,
[all …]
H A Dpowerdomains44xx_data.c38 .banks = 5,
63 .banks = 1,
81 .banks = 2,
101 .banks = 1,
119 .banks = 3,
140 .banks = 1,
157 .banks = 1,
174 .banks = 1,
190 .banks = 1,
207 .banks = 3,
[all …]
H A Dpowerdomains54xx_data.c36 .banks = 5,
62 .banks = 2,
91 .banks = 1,
109 .banks = 1,
126 .banks = 1,
142 .banks = 1,
159 .banks = 2,
188 .banks = 3,
209 .banks = 1,
227 .banks = 2,
[all …]
H A Dpowerdomains3xxx_data.c37 .banks = 4,
59 .banks = 1,
75 .banks = 1,
100 .banks = 2,
122 .banks = 2,
139 .banks = 2,
156 .banks = 1,
171 .banks = 1,
192 .banks = 1,
207 .banks = 1,
[all …]
H A Dpowerdomains2xxx_data.c31 .banks = 1,
46 .banks = 1,
61 .banks = 3,
87 .banks = 1,
H A Dpowerdomains43xx_data.c23 .banks = 1,
37 .banks = 3,
65 .banks = 1,
95 .banks = 4,
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json581 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
586 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
750 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
755 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
760 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
765 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
770 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
775 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
780 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
785 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 1
[all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json543 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
548 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
712 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
717 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
722 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
727 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
732 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
737 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
742 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
747 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
[all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json572 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
577 "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
741 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
746 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
751 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
756 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
761 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
766 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
771 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
776 "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_nvm.c281 struct ice_bank_info *banks = &hw->flash.banks; in ice_get_flash_bank_offset() local
288 offset = banks->nvm_ptr; in ice_get_flash_bank_offset()
289 size = banks->nvm_size; in ice_get_flash_bank_offset()
290 active_bank = banks->nvm_bank; in ice_get_flash_bank_offset()
293 offset = banks->orom_ptr; in ice_get_flash_bank_offset()
294 size = banks->orom_size; in ice_get_flash_bank_offset()
295 active_bank = banks->orom_bank; in ice_get_flash_bank_offset()
298 offset = banks->netlist_ptr; in ice_get_flash_bank_offset()
299 size = banks->netlist_size; in ice_get_flash_bank_offset()
300 active_bank = banks->netlist_bank; in ice_get_flash_bank_offset()
[all …]
/linux/arch/powerpc/platforms/embedded6xx/
H A Dmpc10x.h107 #define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */
108 #define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */
109 #define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */
110 #define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */
112 #define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */
113 #define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */
114 #define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */
115 #define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json643 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
812 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
822 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
832 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
842 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
852 "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
1021 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
1031 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
1041 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
1051 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
[all …]
/linux/drivers/memory/
H A Dfsl_ifc.c42 * This function walks IFC banks comparing "Base address" field of the CSPR
54 for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) { in fsl_ifc_find()
199 * resources for the NAND banks themselves are allocated
205 int version, banks; in fsl_ifc_ctrl_probe() local
235 banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8; in fsl_ifc_ctrl_probe()
236 dev_info(&dev->dev, "IFC version %d.%d, %d banks\n", in fsl_ifc_ctrl_probe()
237 version >> 24, (version >> 16) & 0xf, banks); in fsl_ifc_ctrl_probe()
240 fsl_ifc_ctrl_dev->banks = banks; in fsl_ifc_ctrl_probe()
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-memory.json1019 "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
1188 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
1198 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
1208 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
1218 "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
1228 "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
1397 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
1407 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
1417 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
1427 "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dsamsung,pinctrl-gpio-bank.yaml31 For GPIO banks supporting external GPIO interrupts or external wake-up
37 For GPIO banks supporting external GPIO interrupts or external wake-up
42 For GPIO banks supporting direct external wake-up interrupts (without
H A Dpinctrl-st.txt16 First type is via irqmux, single interrupt is used by multiple gpio banks. This
17 reduces number of overall interrupts numbers required. All these banks belong to
44 with other gpio banks via irqmux.
45 a irqline and gpio banks.
/linux/drivers/clk/tegra/
H A Dclk.c213 static int tegra_clk_periph_ctx_init(int banks) in tegra_clk_periph_ctx_init() argument
215 periph_state_ctx = kcalloc(2 * banks, sizeof(*periph_state_ctx), in tegra_clk_periph_ctx_init()
223 struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) in tegra_clk_init() argument
227 if (WARN_ON(banks > ARRAY_SIZE(periph_regs))) in tegra_clk_init()
230 periph_clk_enb_refcnt = kzalloc_objs(*periph_clk_enb_refcnt, 32 * banks); in tegra_clk_init()
234 periph_banks = banks; in tegra_clk_init()
245 if (tegra_clk_periph_ctx_init(banks)) { in tegra_clk_init()
/linux/Documentation/devicetree/bindings/gpio/
H A Dbrcm,kona-gpio.yaml11 support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
35 GPIO banks on the SoC. The interrupts must be ordered by bank, starting
36 with bank 0. There is always a 1:1 mapping between banks and IRQs.
/linux/drivers/phy/mediatek/
H A DKconfig37 different banks layout, the T-PHY with shared banks between
39 so you can easily distinguish them by banks layout.
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_vf_isr.c168 struct adf_etr_bank_data *bank = &etr_data->banks[0]; in adf_isr()
207 tasklet_init(&priv_data->banks[0].resp_handler, adf_response_handler, in adf_setup_bh()
208 (unsigned long)priv_data->banks); in adf_setup_bh()
216 tasklet_disable(&priv_data->banks[0].resp_handler); in adf_cleanup_bh()
217 tasklet_kill(&priv_data->banks[0].resp_handler); in adf_cleanup_bh()
/linux/drivers/iommu/
H A Dmsm_iommu.h33 /* Maximum number of context banks that can be present in IOMMU */
38 * ncb Number of context banks present on this IOMMU HW instance
46 * context_map: Bitmap to track allocated context banks
/linux/drivers/gpio/
H A Dgpio-bcm-kona.c89 struct bcm_kona_gpio_bank banks[] __counted_by(num_bank);
105 struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id]; in bcm_kona_gpio_lock_gpio()
128 struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id]; in bcm_kona_gpio_unlock_gpio()
588 dev_err(dev, "Couldn't determine # GPIO banks\n"); in bcm_kona_gpio_probe()
591 return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n"); in bcm_kona_gpio_probe()
594 kona_gpio = devm_kzalloc(dev, struct_size(kona_gpio, banks, ret), GFP_KERNEL); in bcm_kona_gpio_probe()
601 dev_err(dev, "Too many GPIO banks configured (max=%d)\n", in bcm_kona_gpio_probe()
627 bank = &kona_gpio->banks[i]; in bcm_kona_gpio_probe()
648 bank = &kona_gpio->banks[i]; in bcm_kona_gpio_probe()

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