Home
last modified time | relevance | path

Searched full:bank (Results 1 – 25 of 1167) sorted by relevance

12345678910>>...47

/linux/drivers/gpio/
H A Dgpio-rockchip.c83 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
86 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
88 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
94 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
97 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
100 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
108 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
112 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
115 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit()
130 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_stat() argument
35 return READ_CSR_STAT(csr_base_addr, bank); in read_csr_stat()
[all …]
H A Dadf_gen4_hw_csr_data.h37 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
39 ADF_RING_BUNDLE_SIZE * (bank) + \
41 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
43 ADF_RING_BUNDLE_SIZE * (bank) + \
45 #define READ_CSR_STAT(csr_base_addr, bank) \ argument
47 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_STAT)
48 #define READ_CSR_UO_STAT(csr_base_addr, bank) \ argument
50 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_UO_STAT)
51 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
53 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
[all …]
H A Dadf_transport.c40 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
42 spin_lock(&bank->lock); in adf_reserve_ring()
43 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
44 spin_unlock(&bank->lock); in adf_reserve_ring()
47 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
48 spin_unlock(&bank->lock); in adf_reserve_ring()
52 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
54 spin_lock(&bank->lock); in adf_unreserve_ring()
55 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
56 spin_unlock(&bank->lock); in adf_unreserve_ring()
[all …]
H A Dadf_gen2_hw_csr_data.c11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
35 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
[all …]
H A Dadf_gen2_hw_csr_data.h30 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
[all …]
H A Dadf_transport_debug.c44 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
45 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show()
46 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show()
51 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_ring_show()
53 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_ring_show()
55 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
60 seq_printf(sfile, "ring num %d, bank num %d\n", in adf_ring_show()
61 ring->ring_number, ring->bank->bank_number); in adf_ring_show()
104 ring->bank->bank_debug_dir, in adf_ring_debugfs_add()
121 struct adf_etr_bank_data *bank = sfile->private; in adf_bank_start() local
[all …]
H A Dadf_gen4_hw_data.c235 "ring pair reset for bank:%d\n", bank_number); in adf_gen4_ring_pair_reset()
396 * adf_gen4_bank_quiesce_coal_timer() - quiesce bank coalesced interrupt timer
398 * @bank_idx: Offset to the bank within this device
401 * This function tries to quiesce the coalesced interrupt timer of a bank if
438 "wait for bank %d - coalesced timer expires in %llu us (max=%u ms estat=0x%x intcolen=0x%x)\n", in adf_gen4_bank_quiesce_coal_timer()
446 "coalesced timer for bank %d expired (%llu us)\n", in adf_gen4_bank_quiesce_coal_timer()
481 dev_dbg(&GET_DEV(accel_dev), "Drain bank %d\n", bank_number); in adf_gen4_bank_drain_start()
485 dev_err(&GET_DEV(accel_dev), "Bank drain failed (timeout)\n"); in adf_gen4_bank_drain_start()
487 dev_dbg(&GET_DEV(accel_dev), "Bank drain successful\n"); in adf_gen4_bank_drain_start()
493 u32 bank, struct bank_state *state, u32 num_rings) in bank_state_save() argument
[all …]
/linux/tools/testing/selftests/gpio/
H A Dgpio-sim.sh25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
38 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE || \
43 rmdir $CONFIGFS_DIR/$CHIP/$BANK
57 local BANK=$2
59 mkdir $CONFIGFS_DIR/$CHIP/$BANK
64 local BANK=$2
[all …]
/linux/drivers/pinctrl/renesas/
H A Dsh_pfc.h442 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
443 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
444 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
446 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
447 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
448 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
449 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument
451 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
452 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
453 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json235 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
245 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
255 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
265 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
590 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
595 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
599 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
604 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
609 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
614 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
[all …]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json198 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
208 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
218 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
228 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
553 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
558 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
562 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
567 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
572 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
577 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
[all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json227 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
237 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
247 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
257 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
582 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
587 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
591 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
596 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
601 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
606 "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
[all …]
/linux/drivers/net/phy/mscc/
H A Dmscc_macsec.c23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write()
75 bank &= 0x3; in vsc8584_macsec_phy_write()
[all …]
/linux/drivers/bus/
H A Duniphier-system-bus.c23 #define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
25 #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff /* data to squash bank 0, 1 */
35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
44 "range found: bank = %d, addr = %08x, paddr = %08llx, size = %08x\n", in uniphier_system_bus_add_bank()
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
52 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank()
54 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank()
[all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json263 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
274 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
285 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
296 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
653 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
662 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
672 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
682 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
692 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
702 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-s3c64xx.c213 * @bank: pin bank related to the domain
217 struct samsung_pin_bank *bank; member
281 struct samsung_pin_bank *bank, int pin) in s3c64xx_irq_set_function() argument
283 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c64xx_irq_set_function()
291 reg = d->virt_base + bank->pctl_offset; in s3c64xx_irq_set_function()
294 /* 4-bit bank type with 2 con regs */ in s3c64xx_irq_set_function()
302 raw_spin_lock_irqsave(&bank->slock, flags); in s3c64xx_irq_set_function()
306 val |= bank->eint_func << shift; in s3c64xx_irq_set_function()
309 raw_spin_unlock_irqrestore(&bank->slock, flags); in s3c64xx_irq_set_function()
318 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_set_mask() local
[all …]
H A Dpinctrl-samsung.h85 * @EINT_TYPE_NONE: bank does not support external interrupts
86 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
87 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
88 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
91 * in a pin bank can support external gpio interrupts or external wakeup
125 * struct samsung_pin_bank_type: pin bank type description
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
136 * @type: type of the bank (register offsets and bitfield widths)
137 * @pctl_offset: starting offset of the pin-bank registers.
138 * @pctl_res_idx: index of base address for pin-bank registers.
[all …]
/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-ma35.c335 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_direction_in() local
336 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE; in ma35_gpio_core_direction_in()
347 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_direction_out() local
348 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT; in ma35_gpio_core_direction_out()
349 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE; in ma35_gpio_core_direction_out()
368 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_get() local
369 void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN; in ma35_gpio_core_get()
376 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_set() local
377 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT; in ma35_gpio_core_set()
390 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_to_request() local
[all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-memory.json281 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
292 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
303 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
314 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
1029 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
1038 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
1048 "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
1058 "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
1068 "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
1078 "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-pinctrl.dtsi12 gpa0: gpa0-gpio-bank {
20 gpa1: gpa1-gpio-bank {
28 gpa2: gpa2-gpio-bank {
36 gpb0: gpb0-gpio-bank {
44 gpb1: gpb1-gpio-bank {
52 gpb2: gpb2-gpio-bank {
60 gpb3: gpb3-gpio-bank {
68 gpc0: gpc0-gpio-bank {
76 gpc3: gpc3-gpio-bank {
84 gpc1: gpc1-gpio-bank {
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-microchip-sgpio.c357 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_pinconf_get() local
359 struct sgpio_priv *priv = bank->priv; in sgpio_pinconf_get()
367 val = bank->is_input; in sgpio_pinconf_get()
371 val = !bank->is_input; in sgpio_pinconf_get()
375 if (bank->is_input) in sgpio_pinconf_get()
392 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_pinconf_set() local
393 struct sgpio_priv *priv = bank->priv; in sgpio_pinconf_set()
406 if (bank->is_input) in sgpio_pinconf_set()
458 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_gpio_set_direction() local
460 return (input == bank->is_input) ? 0 : -EINVAL; in sgpio_gpio_set_direction()
[all …]
/linux/drivers/leds/
H A Dleds-tca6507.c62 * Each bank (BANK0 and BANK1) has two usage counts - LEDs using the
158 /* Bank 2 is Master Intensity and doesn't use times */
159 struct bank { struct
164 } bank[3]; member
175 int bank; /* Bank used, or -1 */ member
275 * bank or other. This can be used for timers, for levels, or for
278 static void set_code(struct tca6507_chip *tca, int reg, int bank, int new) in set_code() argument
282 if (bank) { in set_code()
295 static void set_level(struct tca6507_chip *tca, int bank, int level) in set_level() argument
297 switch (bank) { in set_level()
[all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-memory.json198 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group th…
208 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major …
218 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major …
228 …n channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode i…
542 "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
551 "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
560 "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
569 "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
578 "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
587 "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
[all …]
/linux/Documentation/hwmon/
H A Dabituguru-datasheet.rst60 level we will call banks. A bank holds data for one or more sensors. The data
61 in a bank for a sensor is one or more bytes large.
63 The number of bytes is fixed for a given bank, you should always read or write
65 less then the number of bytes for a given bank are undetermined.
67 See below for all known bank addresses, numbers of sensors in that bank,
71 terminology for the addressing within a bank this is not 100% correct, in
72 bank 0x24 for example the addressing within the bank selects a PWM output not
76 uGuru determines if a read from or a write to the bank is taking place, thus
97 not yet reported 0x08 at DATA and you proceed with writing a bank address.
100 Sending bank and sensor addresses to the uGuru
[all …]

12345678910>>...47