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/linux/drivers/pinctrl/renesas/
H A Dsh_pfc.h1 /* SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
43 const char *name; member
50 .name = #alias, \
56 #define SH_PFC_PIN_GROUP(name) SH_PFC_PIN_GROUP_ALIAS(name, name) argument
62 .name = #_name, \
79 const char *name; member
86 .name = #n, \
92 const char *name; member
99 const char *name; member
[all …]
/linux/tools/testing/selftests/gpio/
H A Dgpio-sim.sh2 # SPDX-License-Identifier: GPL-2.0
6 CONFIGFS_DIR="/sys/kernel/config/gpio-sim"
7 MODULE="gpio-sim"
25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
38 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE || \
43 rmdir $CONFIGFS_DIR/$CHIP/$BANK
[all …]
H A Dgpio-aggregator.sh2 # SPDX-License-Identifier: GPL-2.0
7 CONFIGFS_SIM_DIR="/sys/kernel/config/gpio-sim"
8 CONFIGFS_AGG_DIR="/sys/kernel/config/gpio-aggregator"
9 SYSFS_AGG_DIR="/sys/bus/platform/drivers/gpio-aggregator"
10 MODULE="gpio-aggregator"
24 # gpio-sim
38 local NOCHECK=${1:-0}
41 [ -d "$CHIP_DIR" ] || continue
43 find "$CHIP_DIR" -depth -type d -exec rmdir {} \;
45 [ "$NOCHECK" -eq 1 ] && return;
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.c1 // SPDX-License-Identifier: GPL-2.0+
29 #include <linux/soc/samsung/exynos-pmu.h>
30 #include <linux/soc/samsung/exynos-regs-pmu.h>
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
62 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
67 if (bank->eint_mask_offset) in exynos_irq_mask()
68 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
70 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
72 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
[all …]
H A Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
106 .name = id \
116 .eint_mask = (1 << (pins)) - 1, \
118 .name = id \
130 .name = id \
140 .eint_mask = (1 << (pins)) - 1, \
142 .name = id \
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
64 * There are two registers cfg0 and cfg1 in this style for each bank.
65 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
[all …]
H A Dpinctrl-eyeq5.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * pull-down, pull-up, drive strength and muxing.
10 * that is pin-dependent. Functions are declared statically in this driver.
15 * We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter.
33 #include <linux/pinctrl/pinconf-generic.h>
39 #include "pinctrl-utils.h"
74 * Comments to the right of each pin are the "signal name" in the datasheet.
77 /* Bank A */
110 /* Bank B */
137 /* Bank A */
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H A Dpinctrl-pistachio.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
58 #define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank)) argument
75 const char *name; member
86 const char *name; member
495 .name = #_name, \
502 .name = #_name, \
513 PISTACHIO_FUNCTION_NONE = -1,
637 .name = #_name, \
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H A Dpinctrl-falcon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-falcon.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
22 #include "pinctrl-lantiq.h"
53 .name = #a, \
65 .name = a, \
93 static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len) in lantiq_load_pin_desc() argument
95 int base = bank * PINS; in lantiq_load_pin_desc()
100 d[i].name = kasprintf(GFP_KERNEL, "io%d", base + i); in lantiq_load_pin_desc()
102 pad_count[bank] = len; in lantiq_load_pin_desc()
[all …]
/linux/drivers/uio/
H A Duio_fsl_elbc_gpcm.c1 // SPDX-License-Identifier: GPL-2.0
9 using the general purpose chip-select mode (GPCM).
17 compatible = "fsl,elbc-gpcm-uio";
19 elbc-gpcm-br = <0xff810800>;
20 elbc-gpcm-or = <0xffff09f7>;
21 interrupt-parent = <&mpic>;
25 netx5152,init-win0-offset = <0x0>;
29 Only the entries reg (to identify bank) and elbc-gpcm-* (initial BR/OR
31 are optional (as well as any type-specific options such as
32 netx5152,init-win0-offset). As long as no interrupt handler is needed,
[all …]
/linux/arch/x86/kernel/cpu/mce/
H A Damd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
81 u8 sysfs_id; /* Value used for sysfs name. */
131 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
135 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
138 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
139 if (!b->hwid) in smca_get_bank_type()
142 return b->hwid->bank_type; in smca_get_bank_type()
212 * So to define a unique name for each bank, we use a temp c-string to append
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
28 [irqN]----> [gpio-bank (n)]
[all …]
H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
[all …]
/linux/drivers/pinctrl/meson/
H A Dpinctrl-meson.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * struct meson_pmx_group - a pinmux group
22 * @name: group name
31 const char *name; member
38 * struct meson_pmx_func - a pinmux function
40 * @name: function name
45 const char *name; member
51 * struct meson_reg_desc - a register descriptor
57 * pull-enable, direction, etc. for a single pin
65 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
[all …]
H A Dpinctrl-meson-axg-pmx.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Second generation of pinmux driver for Amlogic Meson-AXG SoC.
14 * Meson-AXG SoC and later series, which use 4-width continuous
25 #include "pinctrl-meson.h"
26 #include "pinctrl-meson-axg-pmx.h"
30 const struct meson_pmx_bank **bank) in meson_axg_pmx_get_bank() argument
33 const struct meson_axg_pmx_data *pmx = pc->data->pmx_data; in meson_axg_pmx_get_bank()
35 for (i = 0; i < pmx->num_pmx_banks; i++) in meson_axg_pmx_get_bank()
36 if (pin >= pmx->pmx_banks[i].first && in meson_axg_pmx_get_bank()
37 pin <= pmx->pmx_banks[i].last) { in meson_axg_pmx_get_bank()
[all …]
/linux/drivers/leds/
H A Dleds-tca6507.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * leds-tca6507
9 * blink or double-blink.
12 * out-only (pull-up resistor required) or as an LED with variable
13 * brightness and hardware-assisted blinking.
21 * with separate time for rise, on, fall, off and second-off. Thus if
22 * 3 or more different non-trivial rates are required, software must
25 * support double-blink so 'second-off' always matches 'off'.
42 * delays in the ranges: 56-72, 112-144, 168-216, 224-27504,
43 * 28560-36720.
[all …]
/linux/drivers/mtd/devices/
H A Dspear_smi.c97 char *name; member
107 .name = n, \
157 * struct spear_smi - Structure for SMI Device
165 * @cmd_complete: queue to wait for command completion of NOR-flash.
167 * @flash: separate structure for each Serial NOR-flash attached to SMI.
182 * struct spear_snor_flash - Structure for Serial NOR Flash
184 * @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
185 * @dev_id: Device ID of NOR-flash.
187 * @mtd: MTD info for each NOR-flash.
188 * @num_parts: Total number of partition in each bank of NOR-flash.
[all …]
/linux/arch/arm/mach-omap2/
H A Dpowerdomain.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
6 * Copyright (C) 2007-2011 Nokia Corporation
10 * XXX This should be moved to the mach-omap2/ directory at the earliest
45 * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
47 * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
48 * bank 1 position. This is true for OMAP3430
50 * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
58 * Number of memory banks that are power-controllable. On OMAP4430, the
77 * struct powerdomain - OMAP powerdomain
[all …]
/linux/drivers/edac/
H A Dqcom_edac.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/soc/qcom/llcc-qcom.h>
60 .name = "DRAM Single-bit",
67 .name = "DRAM Double-bit",
74 .name = "TRAM Single-bit",
81 .name = "TRAM Double-bit",
98 ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable, in qcom_llcc_core_setup()
104 ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->trp_interrupt_0_enable, in qcom_llcc_core_setup()
111 ret = regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_ecc_error_cfg, in qcom_llcc_core_setup()
116 ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable, in qcom_llcc_core_setup()
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_transport_internal.h1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
19 struct adf_etr_bank_data *bank; member
39 spinlock_t lock; /* protects bank data struct */
53 int adf_bank_debugfs_add(struct adf_etr_bank_data *bank);
54 void adf_bank_debugfs_rm(struct adf_etr_bank_data *bank);
55 int adf_ring_debugfs_add(struct adf_etr_ring_data *ring, const char *name);
58 static inline int adf_bank_debugfs_add(struct adf_etr_bank_data *bank) in adf_bank_debugfs_add() argument
63 #define adf_bank_debugfs_rm(bank) do {} while (0) argument
66 const char *name) in adf_ring_debugfs_add() argument
/linux/arch/arm/boot/dts/st/
H A Dstih407-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "st-pincfg.h"
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /* 0-5: PIO_SBC */
18 /* 10-19: PIO_FRONT0 */
31 /* 30-35: PIO_REAR */
38 /* 40-42: PIO_FLASH */
45 pin-controller-sbc@961f080 {
46 #address-cells = <1>;
47 #size-cells = <1>;
[all …]
/linux/drivers/gpio/
H A Dgpio-74x164.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
38 return spi_write(to_spi_device(chip->gpio_chip.parent), chip->buffer, in __gen_74x164_write_config()
39 chip->registers); in __gen_74x164_write_config()
45 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_get_value() local
48 guard(mutex)(&chip->lock); in gen_74x164_get_value()
50 return !!(chip->buffer[bank] & BIT(pin)); in gen_74x164_get_value()
57 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_value() local
60 guard(mutex)(&chip->lock); in gen_74x164_set_value()
63 chip->buffer[bank] |= BIT(pin); in gen_74x164_set_value()
[all …]
H A Dgpio-adp5585.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * Bank 0 covers pins "GPIO 1/R0" to "GPIO 6/R5", numbered 0 to 5 by the
25 * driver, and bank 1 covers pins "GPIO 7/C0" to "GPIO 11/C4", numbered 6 to
31 #define ADP5585_BIT(n) ((n) >= 6 ? BIT((n) - 6) : BIT(n))
34 * Bank 0 covers pins "GPIO 1/R0" to "GPIO 8/R7", numbered 0 to 7 by the
35 * driver, bank 1 covers pins "GPIO 9/C0" to "GPIO 16/C7", numbered 8 to
36 * 15 and bank 3 covers pins "GPIO 17/C8" to "GPIO 19/C10", numbered 16 to 18.
42 int (*bank)(unsigned int off); member
92 const struct adp5585_gpio_chip *info = adp5585_gpio->info; in adp5585_gpio_get_direction()
95 regmap_read(adp5585_gpio->regmap, info->gpio_dir_a + info->bank(off), &val); in adp5585_gpio_get_direction()
[all …]
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sunxi.c6 * Maxime Ripard <maxime.ripard@free-electrons.com>
28 #include <linux/pinctrl/pinconf-generic.h>
33 #include <dt-bindings/pinctrl/sun4i-a10.h>
36 #include "pinctrl-sunxi.h"
50 * for each bank in the following order:
51 * - Mux config
52 * - Data value
53 * - Drive level
54 * - Pull direction
63 * When using the extended register layout, Bank K does not fit into the
[all …]
/linux/Documentation/hwmon/
H A Dw83795.rst10 Addresses scanned: I2C 0x2c - 0x2f
18 Addresses scanned: I2C 0x2c - 0x2f
23 - Wei Song (Nuvoton)
24 - Jean Delvare <jdelvare@suse.de>
28 -----------
35 - W83795G
38 Pin Name Register Sysfs attribute
75 41 FANCTL1 10h (bank 2) pwm1
76 43 FANCTL2 11h (bank 2) pwm2
77 45 FANCTL3 12h (bank 2) pwm3
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