1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/soc/qcom/llcc-qcom.h>
60 		.name = "DRAM Single-bit",
67 		.name = "DRAM Double-bit",
74 		.name = "TRAM Single-bit",
81 		.name = "TRAM Double-bit",
98 	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,  in qcom_llcc_core_setup()
104 	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->trp_interrupt_0_enable,  in qcom_llcc_core_setup()
111 	ret = regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_ecc_error_cfg,  in qcom_llcc_core_setup()
116 	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,  in qcom_llcc_core_setup()
122 	ret = regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_interrupt_enable,  in qcom_llcc_core_setup()
136 		ret = regmap_write(drv->bcast_regmap,  in qcom_llcc_clear_error_status()
137 				   drv->edac_reg_offset->drp_interrupt_clear,  in qcom_llcc_clear_error_status()
142 		ret = regmap_write(drv->bcast_regmap,  in qcom_llcc_clear_error_status()
143 				   drv->edac_reg_offset->drp_ecc_error_cntr_clear,  in qcom_llcc_clear_error_status()
150 		ret = regmap_write(drv->bcast_regmap,  in qcom_llcc_clear_error_status()
151 				   drv->edac_reg_offset->trp_interrupt_0_clear,  in qcom_llcc_clear_error_status()
156 		ret = regmap_write(drv->bcast_regmap,  in qcom_llcc_clear_error_status()
157 				   drv->edac_reg_offset->trp_ecc_error_cntr_clear,  in qcom_llcc_clear_error_status()
163 		ret = -EINVAL;  in qcom_llcc_clear_error_status()
179 	const struct llcc_edac_reg_offset *edac_reg_offset = drv->edac_reg_offset;  in get_reg_offsets()
183 		syn_regs->synd_reg = edac_reg_offset->drp_ecc_sb_err_syn0;  in get_reg_offsets()
184 		syn_regs->count_status_reg = edac_reg_offset->drp_ecc_error_status1;  in get_reg_offsets()
185 		syn_regs->ways_status_reg = edac_reg_offset->drp_ecc_error_status0;  in get_reg_offsets()
188 		syn_regs->synd_reg = edac_reg_offset->drp_ecc_db_err_syn0;  in get_reg_offsets()
189 		syn_regs->count_status_reg = edac_reg_offset->drp_ecc_error_status1;  in get_reg_offsets()
190 		syn_regs->ways_status_reg = edac_reg_offset->drp_ecc_error_status0;  in get_reg_offsets()
193 		syn_regs->synd_reg = edac_reg_offset->trp_ecc_sb_err_syn0;  in get_reg_offsets()
194 		syn_regs->count_status_reg = edac_reg_offset->trp_ecc_error_status1;  in get_reg_offsets()
195 		syn_regs->ways_status_reg = edac_reg_offset->trp_ecc_error_status0;  in get_reg_offsets()
198 		syn_regs->synd_reg = edac_reg_offset->trp_ecc_db_err_syn0;  in get_reg_offsets()
199 		syn_regs->count_status_reg = edac_reg_offset->trp_ecc_error_status1;  in get_reg_offsets()
200 		syn_regs->ways_status_reg = edac_reg_offset->trp_ecc_error_status0;  in get_reg_offsets()
207 dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type)  in dump_syn_reg_values()  argument
218 		ret = regmap_read(drv->regmaps[bank], synd_reg,  in dump_syn_reg_values()
224 			    reg_data.name, i, synd_val);  in dump_syn_reg_values()
227 	ret = regmap_read(drv->regmaps[bank], regs.count_status_reg,  in dump_syn_reg_values()
235 		    reg_data.name, err_cnt);  in dump_syn_reg_values()
237 	ret = regmap_read(drv->regmaps[bank], regs.ways_status_reg,  in dump_syn_reg_values()
246 		    reg_data.name, err_ways);  in dump_syn_reg_values()
253 dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)  in dump_syn_reg()  argument
255 	struct llcc_drv_data *drv = edev_ctl->dev->platform_data;  in dump_syn_reg()
258 	ret = dump_syn_reg_values(drv, bank, err_type);  in dump_syn_reg()
264 		edac_device_handle_ce(edev_ctl, 0, bank,  in dump_syn_reg()
268 		edac_device_handle_ue(edev_ctl, 0, bank,  in dump_syn_reg()
272 		edac_device_handle_ce(edev_ctl, 0, bank,  in dump_syn_reg()
276 		edac_device_handle_ue(edev_ctl, 0, bank,  in dump_syn_reg()
280 		ret = -EINVAL;  in dump_syn_reg()
291 	struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data;  in llcc_ecc_irq_handler()
297 	for (i = 0; i < drv->num_banks; i++) {  in llcc_ecc_irq_handler()
298 		ret = regmap_read(drv->regmaps[i], drv->edac_reg_offset->drp_interrupt_status,  in llcc_ecc_irq_handler()
313 		ret = regmap_read(drv->regmaps[i], drv->edac_reg_offset->trp_interrupt_0_status,  in llcc_ecc_irq_handler()
339 	struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;  in qcom_llcc_edac_probe()
341 	struct device *dev = &pdev->dev;  in qcom_llcc_edac_probe()
345 	if (!llcc_driv_data->ecc_irq_configured) {  in qcom_llcc_edac_probe()
346 		rc = qcom_llcc_core_setup(llcc_driv_data, llcc_driv_data->bcast_regmap);  in qcom_llcc_edac_probe()
352 	edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",  in qcom_llcc_edac_probe()
353 					      llcc_driv_data->num_banks, 1,  in qcom_llcc_edac_probe()
357 		return -ENOMEM;  in qcom_llcc_edac_probe()
359 	edev_ctl->dev = dev;  in qcom_llcc_edac_probe()
360 	edev_ctl->mod_name = dev_name(dev);  in qcom_llcc_edac_probe()
361 	edev_ctl->dev_name = dev_name(dev);  in qcom_llcc_edac_probe()
362 	edev_ctl->ctl_name = "llcc";  in qcom_llcc_edac_probe()
363 	edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;  in qcom_llcc_edac_probe()
366 	ecc_irq = llcc_driv_data->ecc_irq;  in qcom_llcc_edac_probe()
378 	edev_ctl->poll_msec = ECC_POLL_MSEC;  in qcom_llcc_edac_probe()
379 	edev_ctl->edac_check = llcc_ecc_check;  in qcom_llcc_edac_probe()
396 	struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev);  in qcom_llcc_edac_remove()
398 	edac_device_del_device(edev_ctl->dev);  in qcom_llcc_edac_remove()
403 	{ .name = "qcom_llcc_edac" },
412 		.name = "qcom_llcc_edac",