| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | xilinx_can.txt | 1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
10 - reg : Physical base address and size of the controller
12 - interrupts : Property with a value describing the interrupt
14 - clock-names : List of input clock names
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| H A D | xilinx,can.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/xilin
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| /freebsd/sys/contrib/device-tree/Bindings/dma/xilinx/ |
| H A D | xilinx_dma.txt | 1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
2 It can be configured to have one channel or two channels. If configured
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7 target devices. It can be configured to have one channel or two channels.
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
15 target devices. It can be configured to have up to 16 independent transmit
19 - compatibl
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| /freebsd/sys/contrib/device-tree/Bindings/fpga/ |
| H A D | xlnx,pr-decoupler.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decouple
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
20 later ones are described in this binding. Each clock domain can be also
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| H A D | adi,axi-clkgen.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
10 - Lars-Peter Clausen <lars@metafoo.de>
11 - Michael Hennerich <michael.hennerich@analog.com>
15 that can be synthesized on various FPGA platforms.
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
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| H A D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-cc
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| /freebsd/sys/contrib/device-tree/Bindings/hwmon/ |
| H A D | adi,axi-fan-control.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/adi,axi
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | xilinx-xadc.txt | 6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
10 on all series 7 platforms and is a softmacro with a AXI interface. This binding
16 communication. Xilinx provides a standard IP core that can be used to access the
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | adi,axi-i2s.txt | 1 ADI AXI-I2S controller
3 The core can be generated with transmit (playback), only receive
7 - compatible : Must be "adi,axi-i2s-1.00.a"
8 - reg : Must contain I2S core's registers location and length
9 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
10 The controller expects two clocks, the clock used for the AXI interface and
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
14 - dmas: Pairs of phandle and specifier for the DMA channels that are used by
17 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
19 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | brcm,bus-axi.txt | 1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
13 them manually through device tree. Use an interrupt-map to specify the
17 The top-level axi bus may contain children representing attached cores
18 (devices). This is needed since some hardware details can't be auto
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_pcie.c | 1 /*-
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
66 #define AL_PCIE_MIN_MEMORY_BAR_SIZE (1 << 12)
67 #define AL_PCIE_MIN_IO_BAR_SIZE (1 << 8)
72 /** RC - Revisions 1/2 */
77 /** EP - Revisions 1/2 */
82 /** RC - Revision 3 */
87 /** EP - Revision 3 */
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| H A D | al_hal_udma_iofic.h | 1 /*-
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
56 /* *INDENT-OFF* */
60 /* *INDENT-ON* */
69 AL_IOFIC_MODE_LEGACY, /**< level-sensitive interrupt wire */
70 AL_IOFIC_MODE_MSIX_PER_Q, /**< per UDMA queue MSI-X interrupt */
82 * interrupt controller of each bus-master unit in the I/O Fabric.
83 * The first two groups can be used when accessing the secondary interrupt
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| H A D | al_hal_udma_regs_s2m.h | 1 /*-
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
77 /* [0x24] AXI outstanding read configuration */
79 /* [0x28] AXI outstanding write configuration */
86 * 00 - No pending tasks
100 * 0 - Log is enable
101 * 1 - Log is masked.
131 /* [0x30] S2M AXI data FIFO status */
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| H A D | al_hal_pcie_interrupts.h | 1 /*-
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
48 * The PCIe interrupts HAL can be used to control PCIe unit interrupts.
49 * There are 5 groups of interrupts: app group A, B, C, D and AXI.
51 * 1. Summary for all the int groups (AXI+APP CORE).
73 * App group A interrupts mask - don't change
80 AL_PCIE_APP_INT_DEASSERT_INTC = AL_BIT(1),
84 * [RC only] Deassert_INTA received - there's a dedicated GIC interrupt
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| H A D | al_hal_udma_regs_m2s.h | 1 /*-
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
77 /* [0x24] AXI outstanding configuration */
84 * 00 - No pending tasks
98 * 0 - Log is enabled.
99 * 1 - Log is masked.
213 * 0 - Rate limit is active.
214 * 1 - Rate limit is masked.
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| H A D | al_hal_pcie_axi_reg.h | 1 /*-
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
148 * [0x28] this register override the Target-ID field in the AXUSER [19:4],
149 * for the AXI master port.
152 /* [0x2c] this register override the ADDR[63:32] AXI master port. */
154 /* [0x30] this register override the ADDR[63:32] AXI master port. */
157 * [0x34] Define the size to replace in the master axi address bits
199 * [0x44] this register override the Target-ID field in the AXUSER [19:4],
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pci
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | snps,dwc-qos-ethernet.txt | 13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qo
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,coresight-catu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
17 specification and can be connected in various topologies to suit a particular
18 SoCs tracing needs. These trace components can generally be classified as
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | nxp,dw100.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
18 The engine can be used to perform scaling, cropping and pixel format
24 - nxp,imx8mp-dw100
27 maxItems: 1
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| H A D | rockchip,vdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
12 description: |-
13 The Rockchip rk3399 has a stateless Video Decoder that can decodes H.264,
19 - const: rockchip,rk3399-vdec
20 - items:
21 - enum:
22 - rockchip,rk3228-vdec
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| /freebsd/sys/riscv/conf/ |
| H A D | NOTES | 2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs.
11 makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
12 makeoptions WITH_CTF=1 # Run ctfconvert(1) for DTrace support
23 # RISC-V SBI console
41 # NOTE: dtrace introduces CDDL-licensed components into the kernel
47 device uart_ns8250 # ns8250-typ
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| /freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
| H A D | of-xilinx-wdt.txt | 1 Xilinx AXI/PLB soft-core watchdog Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or
6 "xlnx,xps-timebase-wdt-1.01.a".
7 - reg : Physical base address and size
10 - clocks : Input clock specifier. Refer to common clock
12 - clock-frequency : Frequency of clock in Hz
13 - xlnx,wdt-enable-once : 0 - Watchdog can be restarted
14 1 - Watchdog can be enabled just once
15 - xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,
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| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | marvell,xenon-sdhci.txt | 11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-ap807-sdhci": For controllers on Armada AP807.
16 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
18 - clocks:
21 CP110, the AXI clock is also mandatory.
23 - clock-names:
26 The input clock for the AXI bus must be named as "axi".
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