Searched +full:axi +full:- +full:1 +full:wire +full:- +full:host (Results 1 – 4 of 4) sorted by relevance
1 /*-2 * SPDX-License-Identifier: ISC4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>5 * Copyright (c) 1999-2015, Broadcom Corporation9 * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's30 * JEDEC JEP-106 Core Vendor IDs32 * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's33 * non-standard 4-bit continutation code), as used in ARM's PrimeCell38 * will need to convert bus-specific vendor IDs to their BHND_MFGID39 * JEP-106 equivalents.[all …]
5 # Date: 2024-11-25 03:15:028 # the PCI ID Project at https://pci-ids.ucw.cz/.14 # (version 2 or higher) or the 3-clause BSD License.25 # device device_name <-- single tab26 # subvendor subdevice subsystem_name <-- two tabs30 # This is a relabelled RTL-813931 8139 AT-2500TX V3 Ethernet41 7a09 PCI-to-PCI Bridge50 7a19 PCI-to-PCI Bridge55 7a29 PCI-to-PCI Bridge[all …]
1 /*-10 found at http://www.gnu.org/licenses/gpl-2.0.html376 * - If MSI-X is enabled and auto_clear control bit =TRUE, automatically377 * cleared after MSI-X message associated with this specific interrupt378 * bit is sent (MSI-X acknowledge is received).379 * - Software can set a bit in this register by writing 1 to the381 * Write-0 clears a bit. Write-1 has no effect.382 * - On CPU Read - If clear_on_read control bit =TRUE, automatically392 * Writing 1 to a bit in this register sets its corresponding cause bit,400 * If Auto-mask control bit =TRUE, automatically set to 1 after MSI-X[all …]
2 * Copyright (c) 2017-2018 Cavium, Inc. 9 * 1. Redistributions of source code must retain the above copyright35 …_K2_E5 (0x1<<1) // It indicates ras…36 …GLCS_REG_INT_STS_RASDP_ERROR_K2_E5_SHIFT 140 …R_K2_E5 (0x1<<1) // This bit masks, …41 …GLCS_REG_INT_MASK_RASDP_ERROR_K2_E5_SHIFT 145 …ROR_K2_E5 (0x1<<1) // It indicates ras…46 …GLCS_REG_INT_STS_WR_RASDP_ERROR_K2_E5_SHIFT 150 …RROR_K2_E5 (0x1<<1) // It indicates ras…51 …GLCS_REG_INT_STS_CLR_RASDP_ERROR_K2_E5_SHIFT 1[all …]